Parallel Short-Blocklength Error Control for High Throughput
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Solution Overview
Problem
High-throughput communication systems face challenges in approaching the Shannon capacity without feedback, particularly in achieving low frame error rates and managing decoder complexity, especially at high throughputs beyond 100 Gbps, where existing error control mechanisms struggle to guarantee performance.
Innovation Solution
The system employs short-blocklength codes transmitted and decoded in parallel, with incremental redundancy delivered only to decoders that need it, using a feedback-less approach to achieve capacity, leveraging central limit theorem arguments and packet-level erasure codes to ensure strong frame error rate guarantees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long-blocklength codes are used to approach Shannon capacity, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments a long-blocklength code into multiple shorter blocklength codes that are decoded in parallel. Instead of decoding one very long block, the system divides the communication block into several shorter blocks, each decoded by a separate decoder operating in parallel. This segmentation maintains the reliability benefits of long blocklengths while reducing the complexity of individual decoders, as each short-blocklength decoder is simpler than a single long-blocklength decoder would be.
2Reliability
If feedback is used to control incremental redundancy transmission, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by having each short-blocklength decoder independently determine whether it needs incremental redundancy based on its own decoding outcome, without requiring central coordination or feedback communication. Each decoder autonomously evaluates its success and requests additional redundancy only when necessary, eliminating the need for complex feedback control mechanisms while maintaining reliability guarantees.
3Device complexity
If short-blocklength codes are used to reduce decoder complexity, then device complexity is reduced, but reliability deteriorates
Solution Approach 1:
The patent merges multiple short-blocklength code decoders into a parallel decoding architecture. While each individual short-blocklength decoder is simple, the system combines multiple such decoders working in parallel on different segments of the communication block. This merging approach achieves the reliability of long-blocklength codes by aggregating the capabilities of multiple short-blocklength decoders, effectively compensating for the shorter blocklength of individual codes through parallel processing.
Data Source
AI summary
A high throughput communication apparatus which provides low frame error rates (FER). Error checking encoder and decoders which each comprise a plurality of short blocklength error checking encoders or decoders, respectively, in parallel, coupled through common incremental redundancy. Short-blocklength codes are utilized to achieve communication capacity with incremental redundancy. The system can transmit and decode a large number of short-blocklength codewords in parallel, while it delivers incremental redundancy, without feedback, only to the decoders that need incremental redundancy.