Parallel Sigma-Delta A/D Converter for Noise and Area Reduction
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Solution Overview
Problem
Conventional Analog-to-Digital (A/D) converters face challenges in achieving high precision and high speed simultaneously due to issues with thermal noise, kickback noise, and capacitor matching precision, leading to increased chip area and power consumption, especially in low supply voltage and deep sub-micron processes.
Innovation Solution
A parallel oversampling algorithmic A/D converter system utilizing multiple sigma-delta modulators with parallel oversampling and residue addition to achieve high precision and speed, where the control unit manages sampling and quantization, and the MSBs and LSBs are calculated separately to reduce noise and matching errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling capacitor capacitance is increased to reduce thermal noise and improve precision, then the S/N ratio is improved, but the chip area and power consumption increase due to larger operational amplifier sizes and bias current
Solution Approach 1:
The patent divides the sampling process into multiple parallel channels, each with its own smaller sampling capacitor. By segmenting the total capacitance requirement across multiple channels and combining their outputs, the system achieves the required noise performance without requiring a single large capacitor, thus reducing chip area and power consumption.
Solution Approach 2:
The patent combines the outputs of multiple parallel oversampling channels to achieve the desired precision. By merging the results from multiple channels each with smaller capacitors, the system attains the equivalent noise performance of a single large capacitor while using smaller individual components, reducing overall chip area and power consumption.
2Measurement precision
If the sampling capacitor capacitance is increased to reduce thermal noise, then the S/N ratio is improved, but the operating speed decreases due to the need for larger driving performance
Solution Approach 1:
The patent segments the sampling function into multiple parallel channels, each handling a portion of the total sampling task. This allows each channel to use smaller capacitors that can be driven at higher speeds, while the parallel architecture maintains the required precision through combination of results, thus achieving both high S/N ratio and high operating speed.
Solution Approach 2:
The patent performs oversampling in multiple parallel channels, where each channel performs more sampling operations than strictly necessary for that individual channel. By combining these partial results, the system achieves high precision without requiring any single channel to use large capacitors, maintaining high operating speed while improving S/N ratio.
3Measurement precision
If the capacitor capacitance is increased to reduce thermal noise, then the S/N ratio is improved, but kickback noise increases in proportion to capacitor capacitance
Solution Approach 1:
The patent segments the total capacitance requirement into multiple smaller capacitors operating in parallel. Each smaller capacitor generates proportionally less kickback noise during switching, and the parallel architecture combines their outputs to achieve the required precision. This segmentation approach maintains high S/N ratio while significantly reducing the kickback noise problem.
4Measurement precision
If the precision is increased to 14 bits or higher, then the measurement precision is improved, but the conversion time increases due to complicated algorithms and more arithmetic operation steps
Solution Approach 1:
The patent segments the high-precision conversion task into multiple parallel channels that simultaneously perform simplified conversion operations. Each channel processes a portion of the precision requirement using simpler algorithms, and the results are combined to achieve the full 14-bit or higher precision. This parallel segmentation dramatically reduces conversion time compared to sequential processing.
Solution Approach 2:
The patent performs partial conversions in parallel across multiple channels, where each channel performs a simplified conversion that contributes to the final high-precision result. By performing these partial actions simultaneously rather than sequentially, the system achieves high precision without the time penalty of complicated sequential algorithms.
5Measurement precision
If the operational amplifier gain is increased to achieve high precision, then the measurement precision is improved, but the operating speed and output range are compromised
Solution Approach 1:
The patent segments the gain requirement across multiple parallel operational amplifiers, where each amplifier operates at moderate gain levels. The parallel architecture combines their outputs to achieve the equivalent of a single high-gain amplifier, but maintains higher operating speeds and wider output ranges since each individual amplifier doesn't need to operate at the extreme gain levels that would compromise speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high precision and high-speed A/D conversion while minimizing chip area and power consumption, and is cost-effective by reducing the need for large capacitors and operational amplifiers, thus overcoming the limitations of existing technologies.
Implementation Method 1
a sampling capacitor Cs which samples the analog input signal
Implementation Method 2
an integrator with an integration capacitor Cf which integrates an output signal of the sampling capacitor Cs
Implementation Method 3
a quantizer which quantizes an output signal of the integrator
Data Source
AI summary
Each of plural sigma-delta modulators having a sampling capacitor, an integrator, and a quantizer are connected to each other in parallel. Each of the sigma-delta modulators conducts parallel oversampling in which an analog input signal is sampled by a sampling capacitor, and the sampling result is quantized by the integrator and the quantizer. Then, the quantized values of the sigma-delta modulators are added to obtain MSBs, the residue values of the integrators after quantizing in the respective sigma-delta modulators are added, and the addition result of the residue values is converted analog-to-digital to obtain LSBs.