Parallel Signal Processing Trigger Synchronization
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Solution Overview
Problem
Existing digital signal-processing devices lack synchronization and accurate timing in parallel-operating signal branches, leading to reduced accuracy in triggering events, especially in decimated signal-processing blocks where the sampling period increases, causing inaccuracies in trigger position determination.
Innovation Solution
The implementation of a signal-processing device with two or more parallel signal branches, where a recording controller drives a trigger-switching element to ensure the same timing period is recorded in both branches, using a switchover device to switch between external and internal trigger signals, and employing trigger-offset registers to account for signal delays and decimation, ensuring synchronous operation and accurate trigger timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If decimation of the digital input signal sequence occurs in signal-processing blocks, then the sampling period increases, but the accuracy of trigger position determination deteriorates
Solution Approach 1:
The patent applies preliminary action by storing the trigger position in a buffer memory before decimation occurs. The trigger position is captured at the higher sampling rate and then transferred to the output signal sequence after decimation, preserving the original trigger position accuracy despite the reduced sampling rate in the output signal.
2Productivity
If parallel signal branches operate independently, then processing speed increases, but synchronization and timing accuracy between branches deteriorate
Solution Approach 1:
The patent merges the timing control of parallel signal branches by using a common trigger signal that is distributed to all branches. The trigger position determined in one branch is used to control the recording and processing in all other branches, ensuring synchronized operation and consistent timing accuracy across all parallel branches while maintaining high processing speed.
Data Source
AI summary
A digital signal-processing device is described which comprises a recording controller for control of recording in the memories drives a trigger-switching element arranged in the trigger line downstream of the two parallel-operating signal-processing units in such a manner that essentially the same timing period is recorded in both memories during a post-triggering period after a trigger time.