Parallel Processor Simulation Scheduling
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Solution Overview
Problem
Complex hardware designs require efficient simulation methods to manage increasing computational complexity and simulation time, especially when dealing with large and interconnected electronic components, where existing methods struggle to achieve high parallelization and memory access efficiency.
Innovation Solution
The method partitions a design verification task into atomic Processing Elements (PEs) with execution dependencies, computes an optimal execution order for concurrent execution on a multiprocessor device, and groups PEs into PE Groups to maximize concurrency and memory access efficiency, using GPUs or other parallel processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simulation is performed using sequential processing, then execution dependencies are easily managed, but simulation time becomes excessively long for large and complex designs
Solution Approach 1:
The verification task is partitioned into multiple atomic Processing Elements (PEs) that can be executed in parallel. Each PE represents an independent unit of work that processes a specific portion of the design, allowing concurrent execution across multiple processors while maintaining manageable execution dependencies within each atomic unit.
Solution Approach 2:
The patent transitions from sequential single-dimensional execution to parallel multi-dimensional execution by distributing PEs across multiple processors. The execution model adds a temporal dimension through phase-based scheduling, where PEs are organized into execution phases that can progress simultaneously on different processors, effectively converting a time-series execution model into a space-time parallel model.
2Productivity
If PEs are highly parallelized across multiple processors, then simulation speed increases, but managing execution dependencies and ensuring correct ordering becomes complex
Solution Approach 1:
The system performs preliminary ordering of PEs before execution by computing an execution order that respects all data dependencies. This pre-computed order is then used to guide the parallel execution phases, allowing the complex dependency management to be resolved in advance rather than during runtime, simplifying the actual execution phase.
Solution Approach 2:
The execution model dynamically organizes PEs into phases based on their dependency relationships. The phase assignment is flexible and adapts to the specific dependency structure of the verification task, allowing the system to optimize parallel execution without requiring rigid static scheduling. Processors can dynamically select which phase to execute next based on completion status.
3Use of energy by moving object
If PEs are grouped into PE Groups for execution, then memory access efficiency improves, but the grouping process adds computational overhead
Solution Approach 1:
The patent merges multiple PEs into PE Groups that are executed together on the same processor during the same phase. This grouping combines memory access patterns from multiple PEs, improving memory utilization and reducing redundant memory operations. The grouping strategy merges PEs with similar memory access characteristics to maximize memory efficiency.
Solution Approach 2:
The system changes the organizational parameter of PEs from individual atomic units to grouped units for execution purposes. This parameter change allows the system to optimize memory access at the group level rather than the individual PE level, reducing memory traffic and improving efficiency. The grouping parameter can be adjusted based on the specific verification task characteristics.
Data Source
AI summary
A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs—108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.