Parallel Recursive Sinusoid Synthesizer for Higher Clock Frequency
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Solution Overview
Problem
Existing digital sinusoid generators face limitations in achieving higher clock frequencies due to long critical paths in their network diagrams, which restrict the rate at which digital sinusoidal values can be generated.
Innovation Solution
The implementation of a scalable processing architecture with optimized core processes that reduce the critical path by using a combination of multipliers and adders, allowing for higher clock frequencies and efficient generation of sinusoidal signals, along with a refresh circuit to manage quantization errors through periodic high-precision value updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a traditional digital sinusoid generator network is used, then the circuit structure is simple, but the critical path is long which limits the clock frequency
Solution Approach 1:
The patent divides the sinusoid generation function into multiple independent core processes (first core process, second core process, etc.), each capable of generating sinusoid values. This segmentation allows parallel execution of multiple core processes to achieve higher effective clock frequencies while each individual core process maintains a manageable critical path length.
Solution Approach 2:
The patent transitions from sequential single-core processing to parallel multi-core processing, adding a dimensional aspect of parallelism. Multiple core processes operate simultaneously on different data streams, effectively increasing the processing throughput and clock frequency capability without proportionally increasing the critical path of individual operations.
2Speed
If multiple digital operations are performed in sequence, then the computation is complete, but the critical path delay increases reducing the operating frequency
Solution Approach 1:
The patent implements preliminary action by pre-computing and storing sinusoid values in lookup tables, and by using a refresh circuit that periodically updates quantization error correction values. This allows the main sinusoid generation to proceed with reduced computational delay, as some operations are performed in advance or corrected periodically rather than in real-time sequence.
Solution Approach 2:
The refresh circuit operates periodically to correct quantization errors, rather than requiring continuous correction for every sinusoid value. This periodic action reduces the critical path delay by performing error correction at intervals rather than at every computation step, maintaining accuracy while improving operating frequency.
3Measurement precision
If quantization is used in digital processing, then the circuit is practical, but quantization errors accumulate reducing signal accuracy
Solution Approach 1:
The patent implements feedback through the refresh circuit that periodically reads the current sinusoid values, computes quantization errors, and applies corrections to the lookup tables or core process outputs. This feedback mechanism continuously monitors and corrects accumulated quantization errors, maintaining signal accuracy without requiring high-precision (and thus slower) processing throughout the entire system.
Solution Approach 2:
The refresh circuit discards accumulated quantization errors by periodically resetting or correcting the sinusoid generation state with high-precision reference values. This allows the system to operate efficiently with quantized arithmetic for most operations while periodically recovering from error accumulation, balancing productivity and measurement precision.
Data Source
AI summary
A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.