Parallel SISO Decoder Layout for Faster LDPC Decoding

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Solution Overview

Problem

Current LDPC error correction systems face inefficiencies in memory usage and processing speed due to high memory requirements and complex permutation handling during iterative decoding processes, particularly in fast architectures.

Innovation Solution

A parallel SISO decoder structure that updates Log-likelihood-ratios in a single operation, utilizing a difference array and current array with low and high resolution memory respectively, and efficiently handling permutations by storing variable nodes in their last accessed permutation, reducing the need for multiple permutation blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If fast LDPC decoder architecture is used to increase processing speed, then decoding speed is improved, but memory requirements and complexity increase

Engineering Contradiction:
Improvedecoding speedVSAvoidmemory requirements
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The decoder is divided into multiple parallel SISO (Soft-In Soft-Out) units that process different portions of the codeword simultaneously. Each SISO unit handles a specific set of parity check equations, allowing the decoding process to be segmented into independent parallel operations that reduce overall memory requirements while maintaining high processing speed

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of parallelism by processing multiple parity equations simultaneously across multiple SISO units. This dimensional expansion of the decoding architecture allows throughput to be increased without proportionally increasing memory resources, as the parallel units share common memory structures through time-multiplexed access patterns

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If traditional two-pass Tanner Graph decoding is used, then decoding accuracy is maintained, but processing time increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Multiple SISO units are merged into a single iterative decoding framework where they collectively perform the functions of both traditional passes. The parallel SISO units process different parity check equations simultaneously and exchange messages through shared memory structures, combining their computational power to achieve accurate decoding in fewer iterative cycles than traditional sequential approaches

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The parallel SISO architecture enables continuous processing of multiple codewords and parity equations without idle cycles. While one SISO unit is computing, others are accessing memory or preparing data, ensuring that all computational resources are continuously utilized. This continuous action maintains decoding accuracy while reducing total processing time through efficient resource utilization

Inventive Principle:
Principle #20Continuity of useful action

3Measurement precision

If high resolution memory is used for all data storage, then measurement precision is improved, but memory capacity requirements increase

Engineering Contradiction:
Improvedata resolutionVSAvoidmemory capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

Different memory structures are assigned different resolution requirements based on their specific functions. The extrinsic information memory requires high resolution to maintain decoding accuracy, while the check message memory and other auxiliary structures use lower resolution. This local differentiation of quality allows the system to maintain necessary precision where critical while reducing overall memory capacity requirements in non-critical areas

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7415659B2SISO decoder
Publication Date: 2008.08.19 COMTECH SATELLITE NETWORK TECH INC
  • US7415659B2 patent drawing
  • US7415659B2 patent drawing
  • US7415659B2 patent drawing

AI summary

The current invention involves a forward error detection system, especially for use with Low Density Parity Check codes. A parallel SISO structure allows the decoder to process multiple parity equations at the same time. There is a new SISO decoder which allows for the updating of the Log-likelihood-ratio's in a single operation, as opposed to the two pass traditionally associated with the Tanner Graph's. In the decoder, there is a mapping structure that correctly aligns the stored estimates, the stored differences and the SISO's. There is also the ability to deal with multiple instances of the same data being processed at the same time. This structure manages the updates and the differences in such a manner that all calculations on a single piece of data that are processed in parallel are incorporated correctly in the new updated estimates.