Parallel Slice Processor Dispatch Logic for Thread Shadowing
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Solution Overview
Problem
In processor architectures, resources can be tied up when pipelines are busy, leading to reduced throughput due to stalled instruction streams, as existing designs often allocate specific resources and pipelines for execution, resulting in inefficiencies when all assigned pipelines are occupied.
Innovation Solution
A circuit arrangement with dynamically-combinable parallel execution slices and dispatch logic that allows for the execution of instructions from multiple streams, including supplemental instructions and support for various threading modes, enabling flexible assignment and partitioning of execution slices to maintain active states even during busy conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If specific resources and pipelines are allocated for execution of different instruction streams, then instruction stream execution is enabled, but resources remain tied up when pipelines are busy, reducing throughput
Solution Approach 1:
The patent implements dynamic resource allocation where execution slices can be reassigned between instruction streams based on real-time pipeline availability. Instead of static allocation, the system dynamically selects which instruction stream receives which execution slice, allowing resources to be freed and reassigned when pipelines become available, thus maintaining high throughput while preserving allocation flexibility.
Solution Approach 2:
The patent creates a universal resource pool where execution slices serve multiple instruction streams rather than being dedicated to single streams. Each execution slice can handle instructions from any instruction stream, and the dispatch logic routes instructions to appropriate slices based on current workload and availability, enabling one resource to perform multiple functions across different instruction streams.
2Reliability
If multiple pipelines are assigned to an instruction stream, then program execution continues during busy conditions, but all pipelines may still become occupied, causing stalls
Solution Approach 1:
The patent merges multiple execution slices into a unified resource pool that serves all instruction streams collectively. Instead of maintaining separate pipeline assignments for each instruction stream, the system combines execution resources and uses centralized dispatch logic to allocate them dynamically, ensuring continuous execution while maximizing overall throughput through coordinated resource sharing.
Solution Approach 2:
The patent introduces dispatch logic as an intermediary between instruction streams and execution slices. This mediator monitors pipeline availability and instruction readiness, making intelligent routing decisions to prevent stalls by directing instructions to available execution slices rather than allowing instruction streams to wait for specific dedicated pipelines.
3Ease of operation
If execution slices are dedicated to specific instruction streams, then instruction execution is simplified, but resource utilization decreases when pipelines are busy
Solution Approach 1:
The patent segments the processor into multiple independent execution slices that can be individually allocated to different instruction streams. Each slice maintains its own execution simplicity while the system as a word achieves high utilization through flexible combination and reassignment of these segmented units based on real-time demand and pipeline availability.
Data Source
AI summary
Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.