Parallel Slice Processor Instruction Dispatch and Reconfiguration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing processor cores face reduced throughput due to resources being tied up in busy pipelines, leading to instruction stream stalls when all assigned pipelines are busy.
Innovation Solution
Implementing a method where instruction execution slices can be dynamically reassigned or combined to handle wider instructions or SIMD operations, allowing subsequent instructions to be dispatched to available slices, even if initially assigned to another instruction stream, thereby avoiding stalls and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If specific resources and pipelines are allocated for execution of different instruction streams, then resource sharing and continuous execution are enabled, but resources remain tied up when pipelines are busy, causing instruction stream stalls
Solution Approach 1:
The patent implements dynamic pipeline allocation where the mapping between instruction streams and execution slices is not fixed but can change based on real-time resource availability. When a pipeline becomes busy, the system dynamically reassigns subsequent instructions to different available pipelines, allowing the instruction stream to adapt its execution path rather than stalling. This dynamic remapping mechanism enables continuous processor productivity while maintaining flexibility in handling multiple instruction streams.
2Reliability
If pipelines are assigned to instruction streams, then execution can proceed during waiting conditions, but all assigned pipelines being busy causes stalls that reduce throughput
Solution Approach 1:
The patent employs a lookahead mechanism that monitors pipeline busy conditions and proactively identifies alternative pipelines before the current pipeline becomes unavailable. When a pipeline is detected to be busy or approaching a stall condition, the system has already prepared alternative execution paths by identifying available pipelines in advance. This preliminary action prevents stalls from occurring and maintains both execution continuity and high throughput by ensuring no instruction stream waits idle.
Data Source
AI summary
A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.