Parallel Sorting Array for SSD Data Streams
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Solution Overview
Problem
Deep learning and neural networks require significant power consumption due to data movement between memory and processing elements, and traditional sorting methods for Single-Shot Detection (SSD) are inefficient, time-consuming, and energy-intensive, especially when handling multiple categories of data.
Innovation Solution
A hardware configuration with a sequence of sorting elements arranged in rows, where each element applies retention logic to select and pass either the larger or smaller value to the next element, allowing for parallel sorting of data streams without the need for extensive random-access memory storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional sorting approaches are used for SSD candidate boxes, then sorting can be performed, but the process becomes time-consuming and energy-intensive
Solution Approach 1:
The patent divides the sorting task into multiple independent streams, each handled by dedicated sorting circuits. Candidate boxes are partitioned by category, and each category undergoes parallel sorting operations. This segmentation enables simultaneous processing of multiple data streams without sequential bottlenecks, dramatically improving sorting speed while reducing overall energy consumption through parallel execution.
Solution Approach 2:
The patent transitions from traditional sequential sorting to a parallel processing architecture that adds the dimension of concurrent execution. Multiple sorting operations occur simultaneously across different category streams, effectively moving from a one-dimensional sequential process to a multi-dimensional parallel process, thereby achieving both speed improvement and energy efficiency.
2Measurement precision
If multiple categories of data are sorted sequentially, then each category can be sorted accurately, but the total processing time increases significantly
Solution Approach 1:
The patent segments the sorting task by category, creating separate sorting circuits for each category (e.g., pedestrian, car, bicycle). Each sorting circuit maintains full sorting accuracy for its assigned category while operating independently. This segmentation allows all categories to be sorted simultaneously rather than sequentially, eliminating the time penalty while preserving sorting precision through dedicated hardware for each category.
Solution Approach 2:
The patent adds the dimension of parallel processing by implementing multiple sorting circuits that operate concurrently. Instead of processing categories one after another in a single time dimension, the system processes multiple categories simultaneously across multiple parallel circuits, effectively transforming the time-space tradeoff and achieving both accuracy and speed.
3Adaptability or versatility
If large amounts of candidate box information are stored in random-access memory, then complete data is available for sorting, but energy consumption increases and memory requirements grow
Solution Approach 1:
The patent extracts only the essential sorting functionality from general-purpose memory systems and implements dedicated sorting circuits that process data streams directly. By taking out the sorting operation from the memory subsystem and implementing it in dedicated hardware, the system eliminates the need to store large amounts of candidate box information in random-access memory, thereby reducing both memory requirements and the energy consumption associated with memory access and storage.
4Productivity
If parallel processing elements are used for sorting, then sorting speed improves, but system complexity and chip area requirements increase
Solution Approach 1:
The patent segments the parallel processing system into identical, modular sorting circuit units, each handling a specific category. This segmentation allows the complex parallel processing task to be divided into simple, repeatable modules that can be implemented using standard cell libraries. Each module has the same structure and functionality, making the overall system easier to design, verify, and manufacture despite the parallel architecture.
Solution Approach 2:
The patent implements universal sorting circuit units that can handle any category of data through parameter configuration rather than structural variation. Each sorting circuit is designed to be category-agnostic, processing data based on configurable parameters such as category identifiers and sorting criteria. This universality reduces system complexity by eliminating the need for specialized circuits for each category, allowing the same hardware block to serve multiple functions across different data streams.
Data Source
AI summary
A processing device having a sequence of sorting elements arranged in an array. Each of the sorting elements stores a previously retained value therein and receives an input value from a previous sorting element. Each sorting element applies retention logic to select one of the input value or the retained value to be passed to the next sorting element in the array. The value that is passed to the next sorting element can either be set to be the larger, or the smaller, of the input value and the previously retained value, as desired. Rows of processing elements in the array operate in parallel such that large data streams are sorted in parallel (with the data values moving down from one row of processing elements to the next row such that the largest, or the smallest, data values accumulating in the final row of processing elements).