Parallel Sorting Registers Merge Transpose Data
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Solution Overview
Problem
Current semi-parallelized and parallelized sorting algorithms on data-parallel devices like GPUs are inefficient for small data sets, experience significant branch divergence, and fail to fully utilize compute capacity, leading to suboptimal performance and resource utilization.
Innovation Solution
A method involving loading data elements into registers of parallel processors, sorting them in parallel, merging the sorted data elements across processors, and transposing and storing the merged data, which allows for efficient parallel processing and minimizes off-chip memory operations, enabling faster and more efficient sorting on both small and large data sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If semi-parallelized and parallelized sorting algorithms are used on data-parallel devices, then sorting speed is improved, but compute capacity utilization deteriorates due to branch divergence and inability to reach peak throughput
Solution Approach 1:
The sorting algorithm is divided into distinct phases: load phase, sort phase, merge phase, and store phase. Each phase is independently optimized and executed by the data-parallel device, allowing full utilization of compute capacity during each segment without branch divergence affecting overall performance
Solution Approach 2:
Data elements are pre-loaded into the data-parallel device's memory before sorting begins. This preliminary loading action ensures that all data is available in high-speed memory, eliminating bottlenecks and allowing the sorting and merging operations to proceed at peak throughput without waiting for data retrieval
2Productivity
If parallel processing is used for sorting, then processing throughput is improved, but memory access efficiency deteriorates due to frequent off-chip memory operations
Solution Approach 1:
The algorithm nests multiple sorting and merging operations within the data-parallel device's memory hierarchy. Data elements remain within the device's fast memory throughout the sorting and merging process, with only final results being stored back. This nested structure eliminates repeated off-chip memory accesses while maintaining high parallel processing throughput
3Adaptability or versatility
If data-parallel devices process small data sets, then parallel processing capability is utilized, but efficiency deteriorates due to device stalling while waiting for data
Solution Approach 1:
The algorithm dynamically adapts to different data set sizes by adjusting the number of processing elements actively engaged in sorting and merging operations. For small data sets, fewer processing elements are utilized, eliminating stalling conditions while maintaining adequate parallelism. The algorithm flexibly scales resource allocation based on the actual workload size
Data Source
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AI summary
Aspects of the disclosure relate to determining relevant content in response to a request for information. One or more computing devices 170 may load data elements into registers 385A-385B, wherein each register is associated with at least one parallel processor in a group of parallel processors 380A-380B. For each of the parallel processors, the data elements loaded in its associated registers may be sorted, in parallel, in descending order. The sorted data elements, for each of the parallel processors, may be merged with the sorted data elements of other processors in the group. The merged and sorted data elements may be transposed and stored.