Parallel Sample Rate Converter Input Formatting and Coefficient Sharing
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Solution Overview
Problem
Current sample rate converters (SRCs) face challenges in efficient input formatting and coefficient selection, particularly in parallel implementation schemes, which can lead to high computational complexity, area costs, and timing issues due to direct interactions between input and output frequencies.
Innovation Solution
The implementation of a sample rate converter with a low-pass filter and a coefficient bank, along with an input formatter that uses variable input offsets and a polyphase structure to efficiently arrange and select samples and coefficients, avoiding direct timing paths and reducing computational complexity through the use of a 'Write-Lead/Read-Lag' scheme and efficient MUXing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a parallel implementation scheme is used for sample rate conversion, then processing speed and productivity are improved, but device complexity and area costs increase due to the need for multiple filter instances and coefficient storage
Solution Approach 1:
The filter is divided into P polyphase sub-filters, where each sub-filter operates at a lower sampling rate. This segmentation allows parallel processing while reducing the computational burden of each individual filter instance, thus improving productivity without proportionally increasing device complexity
Solution Approach 2:
A single coefficient bank serves all P parallel filter lines, and the same filter structure is reused across all phases. This multi-functionality reduces the overall area costs and device complexity compared to having completely separate filter instances for each parallel line
2Ease of operation
If direct timing paths are used between input and output frequencies in parallel SRC, then ease of operation is maintained, but timing issues and reliability worsen due to frequency interactions
Solution Approach 1:
A buffer memory is introduced as an intermediary between the input formatter and the parallel filter lines. This buffer decouples the timing relationships between different clock domains (input rate and output rate), preventing timing issues and metastability while maintaining ease of operation
Solution Approach 2:
The direct timing path is segmented into separate stages: input formatting stage, buffer storage stage, and filter processing stage. Each stage operates at its own clock rate, eliminating direct frequency interactions and improving reliability
3Manufacturing precision
If more coefficients are stored in the coefficient bank for parallel processing, then manufacturing precision is improved, but area costs and device complexity increase
Solution Approach 1:
The coefficient bank is designed to be shared across all P parallel filter lines. Each coefficient set is reused by multiple filter instances at different time periods, which maintains the precision required for accurate filtering while significantly reducing the total area costs compared to having dedicated coefficient storage for each filter line
Data Source
AI summary
A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“Fin”) and output from the SRC at an output rate (“Fout”) equal to Fin*L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tpp input samples to the filter at a given time, wherein Tpp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tpp of the coefficients to the LPF at a given time.