Parallel Stacked Capacitor for High Density Focal Plane Array
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Solution Overview
Problem
As photodetector technology advances, the need for increased resolution leads to smaller pixel sizes, which reduces integration capacitance, impacting device performance, necessitating improved capacitance solutions without increasing detector size.
Innovation Solution
Incorporating an externally integrated capacitor in parallel with the readout integrated circuit's internal capacitor, utilizing a multilayer dielectric and transition metal-containing electrodes to enhance capacitance while maintaining or improving performance even with decreasing pixel pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to increase the number of pixels and improve resolution, then the number of pixels increases, but integration capacitance decreases
Solution Approach 1:
The patent implements a stacked capacitor structure where a first capacitor and a second capacitor are vertically stacked and electrically connected in parallel. The first capacitor is formed within the pixel structure, while the second capacitor is formed above it, effectively nesting one capacitor inside another spatial arrangement. This vertical stacking allows both capacitors to share the same footprint area, thereby increasing total integration capacitance without increasing pixel area, which resolves the contradiction between maintaining high resolution and preserving sufficient capacitance in smaller pixels.
2Measurement precision
If pixel size is reduced to maintain form factor while incorporating more pixels, then the number of pixels increases, but capacitor area decreases
Solution Approach 1:
The patent transitions from a planar capacitor layout to a three-dimensional stacked configuration. By forming capacitors in multiple vertical layers rather than spreading them out horizontally, the design exploits the vertical dimension to increase total capacitor area without increasing the horizontal pixel footprint. This allows more capacitance to be packed into smaller pixels while maintaining the required form factor and resolution.
3Measurement precision
If capacitor size is reduced to match smaller pixel dimensions, then pixel density increases, but integration capacitance is compromised
Solution Approach 1:
The stacked capacitor configuration nests a second capacitor above a first capacitor, with both capacitors electrically connected in parallel. This nesting approach allows the total capacitance to be the sum of both capacitors, effectively compensating for the reduced individual capacitor sizes in smaller pixels. The vertical stacking ensures that even as pixel dimensions shrink, sufficient total integration capacitance is maintained for reliable detector operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains or enhances integration capacitance, allowing for further reductions in pixel size without compromising detector performance, thereby improving imaging resolution and efficiency.
Implementation Method 1
The external capacitor may include a first electrode overlying the readout integrated circuit substrate, and a dielectric material overlying the first electrode. The external capacitor may further include a second electrode overlying the dielectric material.
Implementation Method 2
forming a dielectric material over the first electrode, and forming a second electrode over the dielectric material
Implementation Method 3
The photodetectors may include a reflector material layer overlying the external capacitor, and located below the detector material. The reflector material may be configured to provide electrical coupling of an electrode of the external capacitor with the readout integrated circuit.
Data Source
AI summary
Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor.