Parallel State Machine Lattices for High-Speed Pattern Recognition
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Solution Overview
Problem
Conventional computing systems face inefficiencies in pattern recognition due to the increasing volume of data and number of patterns to be identified, leading to bottlenecks in processing time, especially when using hardware that searches data streams sequentially rather than in parallel.
Innovation Solution
A processor-based system incorporating a state machine engine with finite state machine lattices arranged in a hierarchical parallel configuration, allowing multiple FSMs to analyze the same data in parallel, thereby accelerating pattern recognition processes and handling high-bandwidth data streams efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional sequential pattern recognition is used, then system complexity is low, but processing speed and productivity deteriorate due to computing bottlenecks
Solution Approach 1:
The patent segments the pattern recognition task into multiple parallel circuits, each responsible for detecting specific patterns in the data stream. This segmentation enables simultaneous processing of multiple patterns, dramatically improving productivity while managing complexity through modular design
Solution Approach 2:
The patent transitions from sequential (one-dimensional) pattern recognition to parallel processing by adding temporal and spatial dimensions. Multiple circuits operate simultaneously at different positions in the processing pipeline, effectively moving from a single-threaded to a multi-threaded architectural dimension
2Speed
If multiple circuits operate in parallel to search data streams, then processing speed improves, but intermediate results become larger than original input data causing system issues
Solution Approach 1:
The patent extracts only the essential matching information from parallel circuit operations, discarding redundant intermediate data. Each circuit outputs only its specific pattern match results rather than complete intermediate states, reducing the volume of data that needs to be processed further
Solution Approach 2:
The patent implements partial processing where circuits only process and output data relevant to their specific pattern detection function. This partial action approach avoids generating excessive intermediate results while maintaining parallel processing speed advantages
3Adaptability or versatility
If the number of patterns to search increases, then pattern recognition capability improves, but processing delay increases as each pattern must be searched sequentially
Solution Approach 1:
The patent divides the set of patterns to be detected into multiple segments, with each segment assigned to a dedicated circuit. This segmentation allows all patterns to be searched simultaneously rather than sequentially, eliminating processing delay while maintaining the ability to detect all patterns
Solution Approach 2:
The patent creates a universal parallel processing architecture where multiple circuits can simultaneously handle different pattern types. This multi-functional system can adapt to search for various patterns concurrently, improving both versatility and speed without trade-offs
Data Source
AI summary
An automaton is implemented in a state machine engine. The automaton is configured to observe data from a beginning of an input data stream until a point when an end of data (EOD) signal is seen. Additionally the automaton is configured to report an event only when one and only one occurrence of a target symbol is seen in the input data stream.