Parallel State Machine Engines for High-Bandwidth Pattern Recognition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computing systems are inefficient in performing complex data analysis, particularly in pattern recognition tasks, due to the increasing volume of data and number of patterns to be detected, leading to processing bottlenecks and delays.
Innovation Solution
A processor-based system employing multiple finite state machine engines with hierarchical parallel configuration, where each engine includes finite state machine lattices that analyze data streams in parallel, enabling rapid recognition of complex patterns across high-bandwidth data streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data streams are searched for each pattern one at a time, then pattern recognition accuracy is maintained, but processing speed decreases and data stream throughput is reduced
Solution Approach 1:
The patent divides the pattern recognition task into multiple parallel search pipelines, where each pipeline is dedicated to searching for a specific pattern or set of patterns. This segmentation allows simultaneous processing of multiple patterns without interfering with each other, maintaining accuracy while increasing throughput by eliminating sequential bottlenecks
Solution Approach 2:
The patent transitions from sequential pattern matching (one dimension in time) to parallel pattern matching by introducing multiple search pipelines operating simultaneously. This dimensional change from time-sequential to space-parallel processing enables multiple patterns to be detected concurrently, resolving the contradiction between accuracy and throughput
2Adaptability or versatility
If the number of patterns to be detected increases, then detection capability is improved, but processing delay increases and system performance degrades
Solution Approach 1:
The patent segments the pattern detection task across multiple independent search pipelines, allowing the system to handle an increasing number of patterns by simply adding more pipelines rather than making existing ones more complex. This maintains constant processing delay per pattern while increasing overall detection capability
Solution Approach 2:
The patent performs preliminary organization of patterns into dedicated search pipelines before data processing begins. This pre-configuration allows the system to handle multiple patterns simultaneously from the start, preventing processing delays that would occur if patterns were handled sequentially
3Device complexity
If conventional von Neumann based computers are used for data analysis, then system simplicity is maintained, but processing efficiency for complex patterns is insufficient
Solution Approach 1:
The patent introduces specialized search pipeline hardware as an intermediary component between the conventional von Neumann processor and the data stream. This intermediary handles the computationally intensive pattern matching tasks in parallel, freeing the main processor while maintaining system simplicity through modular architecture
Solution Approach 2:
The patent replaces the mechanical sequential execution model of conventional computers with a parallel processing architecture for pattern recognition. By substituting the sequential von Neumann execution cycle with simultaneous multiple search pipelines, the system achieves superior processing efficiency for complex patterns while maintaining overall system simplicity
Data Source
Figure 1~7
Figure 2
Figure 3
AI summary
An apparatus can include a first state machine engine (14) configured to receive a first portion of a data stream (170) from a processor (12) and a second state machine engine (14) configured to receive a second portion of the data stream (170) from the processor (12). The apparatus includes a buffer interface (136) configured to enable data transfer between the first and second state machine engines (14). The buffer interface (136) includes an interface data bus (376) coupled to the first and second state machine engines (14). The buffer interface (136) is configured to provide data between the first and second state machine engines (14).