Parallel State Version Copying in Multithreaded Processor Lookup Tables

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Solution Overview

Problem

Multithreaded processors face inefficiencies in managing multiple versions of state information, leading to idle time and resource wastage due to the need for separate state registers for each thread, especially when the number of concurrent threads and state information increases.

Innovation Solution

Configurable lookup tables with multiple memory circuits are used to manage state information, allowing for parallel copying or virtual copying of state versions based on the number of items and versions, optimizing storage and access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate state registers are provided for each thread, then each thread can use different versions of state information, but the register space becomes excessively large and expensive

Engineering Contradiction:
Improveability to use different state versionsVSAvoidregister space size
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a copying scheme where state information is copied between versions in a controlled manner. Instead of maintaining separate full copies for each thread, the system copies only necessary state items between versioned storage, reducing overall memory requirements while enabling multiple threads to access different state versions simultaneously

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The state information is divided into individual state items that can be independently versioned and managed. Each state item can have its own version history, allowing the system to track and manage changes at the granular level of individual state parameters rather than treating all state information as a single block

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If the state register is made large enough to accommodate maximum state information for every thread, then all threads can have full state versions, but much of this space is wasted when maximum information is not stored

Engineering Contradiction:
Improvestate information capacityVSAvoidmemory space utilization
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

Different threads can have different amounts of state information based on their specific needs. The system allows each thread to maintain only the state items relevant to its execution, rather than forcing all threads to allocate space for the maximum possible state information. This localized allocation eliminates wasted memory space while maintaining full functionality for each thread

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The state register allocation is dynamic rather than static. Threads can allocate and deallocate state items as needed during execution, and the system automatically manages the versioning and copying of state information. This dynamic approach allows memory usage to adapt to actual thread requirements rather than being constrained by worst-case scenarios

Inventive Principle:
Principle #15Dynamics

3Stability of the object's composition

If the processor waits for all threads to finish before updating state information, then state consistency is maintained, but idle time increases and throughput decreases

Engineering Contradiction:
Improvestate information consistencyVSAvoidprocessor throughput
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The system performs preliminary versioning of state information before thread execution begins. By pre-establishing versioned copies of state data, the system eliminates the need to wait for thread completion before updating state. Threads operate on their assigned state versions independently, allowing state updates to proceed without blocking thread execution, thus maintaining both consistency and high throughput

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7404059B1Parallel copying scheme for creating multiple versions of state information
Publication Date: 2008.07.22 NVIDIA CORP
  • US7404059B1 patent drawing
  • US7404059B1 patent drawing
  • US7404059B1 patent drawing

AI summary

State information in a processor is managed using a lookup table that has multiple memory circuits, each with multiple entries. Items of state information belonging to a first state version are stored in a first group of the entries, with each entry in the first group being in a different one of the memory circuits. To create an updated state version, the items of state information are copied in parallel from the first group of entries to a second group of entries, with each entry in the second group is in a different one of the memory circuits. The copy in the second group of the item being updated is then replaced with the updated value.