Parallel Storage Capacitor for OLED Pixel PPI
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Solution Overview
Problem
In OLED display panels, reducing the layout space for pixels to improve pixel density (PPI) leads to insufficient voltage stabilizing capability due to reduced capacitance values of storage capacitors, as existing pixel circuits like 7T1C or 8T1C structures face challenges in maintaining internal compensation effects.
Innovation Solution
The array substrate incorporates a storage capacitor with two capacitors connected in parallel, where one capacitor includes a storage electrode and a grid electrode of the driving transistor, and the other capacitor includes the storage electrode and a power supply voltage line, with electrodes connected through via holes, allowing for increased capacitance within the same area or reduced area for the same capacitance, enhancing pixel PPI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the layout space for pixels is reduced to improve pixel density, then pixel PPI is improved, but the capacitance value of storage capacitors becomes insufficient
Solution Approach 1:
The storage capacitor is divided into two separate capacitors (first capacitor and second capacitor) that are connected in parallel. The first capacitor uses the grid electrode as one electrode, while the second capacitor uses the power supply voltage line as one electrode. This segmentation allows each capacitor to be independently optimized for capacitance within the reduced pixel area, maintaining voltage stabilizing capability while improving pixel density.
Solution Approach 2:
The patent utilizes vertical layering (z-dimension) by forming capacitors at different levels with insulating layers between them. The first capacitor is formed between the grid electrode and its counter electrode, while the second capacitor is formed between the power supply voltage line and its counter electrode. This three-dimensional arrangement increases the effective capacitance area without increasing the planar footprint, thus improving PPI while maintaining voltage stability.
2Reliability
If the capacitance value is increased to improve voltage stabilizing capability, then voltage stabilizing capability is improved, but the layout space for pixels increases
Solution Approach 1:
The patent merges the functions of two capacitors into a single storage capacitor structure by connecting them in parallel. The first capacitor (grid electrode + counter electrode) and second capacitor (power supply voltage line + counter electrode) work together to provide increased total capacitance. This merging achieves higher voltage stabilizing capability while sharing the same physical space, thus avoiding increase in layout area.
Solution Approach 2:
The counter electrode serves multiple functions: it acts as one electrode for the first capacitor and simultaneously as one electrode for the second capacitor. The insulating layers serve as dielectric materials for both capacitors. This multi-functionality allows the structure to achieve doubled capacitance without proportionally increasing the layout space, as the same structural elements fulfill multiple capacitive roles.
3Reliability
If a dual capacitor structure is used to increase capacitance, then capacitance value is increased, but the device structure becomes more complex
Solution Approach 1:
The patent implements a nested structure where the first capacitor and second capacitor are embedded within the same pixel circuit architecture. The counter electrode for both capacitors can be formed as a single continuous layer, with insulating layers and via holes nested within the existing transistor structure. This nesting approach increases capacitance while minimizing additional structural complexity, as the dual capacitor system integrates seamlessly with the existing pixel circuit layout.
Data Source
AI summary
The disclosure discloses an array substrate, an OLED display panel and a display device. A storage capacitor includes a first capacitor and a second capacitor which are connected in parallel, wherein the first capacitor includes a storage electrode and a first electrode, a layer where the first electrode is located is same as a layer where the grid electrode of the driving transistor is located, the second capacitor includes the storage electrode and a second electrode, a layer where the second electrode is located is same as a layer where the power supply voltage line is located, and the first electrode and the second electrode are electrically connected through a via hole penetrating through a first insulating layer and a second insulating layer.