Parallel Sub-Cache Write Merging to Reduce ECC Timing Overhead
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Solution Overview
Problem
Existing cache systems face challenges in maintaining performance while ensuring fault tolerance due to the timing overhead introduced by error correcting codes (ECC), particularly in high-speed cache memories, which are susceptible to data corruption from cosmic rays and malicious memory accesses.
Innovation Solution
Implementing a caching system with a first and second sub-cache in parallel, where the second sub-cache stores write-miss data and includes line type bits and an eviction controller to manage data flushing and eviction based on these indications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting codes (ECC) are implemented in high speed cache memory to protect against data corruption, then fault tolerance is improved, but timing overhead increases and cache performance deteriorates
Solution Approach 1:
The cache is divided into multiple sets, with each set containing multiple ways. The patent implements selective ECC encoding where only specific ways within a set receive ECC protection, rather than applying ECC uniformly across the entire cache. This segmentation allows the system to maintain fault tolerance for critical data while reducing the overall ECC overhead that would otherwise apply to all cache operations.
Solution Approach 2:
The patent applies different quality levels of error protection to different portions of the cache based on local requirements. Specifically, certain cache ways are configured with ECC encoding while others are not, creating local variations in protection quality. This allows the system to optimize the balance between reliability and performance by providing enhanced protection only where needed, rather than uniformly across the entire cache structure.
2Reliability
If ECC encoding is applied to all cache memory operations, then data protection is improved, but timing overhead increases due to additional checking cycles
Solution Approach 1:
The patent implements partial ECC encoding where only a subset of cache ways within each set are protected with ECC, rather than applying ECC to all cache operations. This partial application of error correction reduces the timing overhead associated with ECC checking and encoding while still providing adequate data protection for the most critical cache locations. The system performs ECC operations on fewer cache lines, thereby reducing the time penalty while maintaining acceptable reliability.
Data Source
AI summary
A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.