Chip Verification with Parallel Sub-TBs and Dedicated Channels
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Solution Overview
Problem
Conventional chip verification methods using a single TestBench (TB) are inefficient when dealing with large logic scales, leading to low simulation efficiency.
Innovation Solution
A chip verification system and method utilizing a management TestBench (TB) and multiple sub-TBs, where each sub-TB is deployed with a different sub-DUT file, allowing for parallel execution and separate transmission channels for different types of information, including a control channel for the head TB, a service channel for the tail TB, and a data channel for intermediate results between sub-TBs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single TestBench (TB) is used for chip verification, then the verification process is simple to manage, but the simulation efficiency is low when the logic scale of the DUT is large
Solution Approach 1:
The verification system is segmented into a management TB and multiple sub-TBs, where each sub-TB handles a specific sub-DUT file. This segmentation allows parallel execution of simulations across multiple sub-TBs, significantly improving simulation efficiency for large logic scale DUTs while maintaining manageable complexity through the coordinating management TB
Solution Approach 2:
The system transitions from a single-threaded verification approach to a multi-dimensional parallel verification architecture. Multiple sub-TBs operate simultaneously in parallel dimensions, each processing different sub-DUT files, while the management TB coordinates across these dimensions through defined communication channels
2Productivity
If multiple sub-TBs are used for parallel verification, then the simulation efficiency is improved, but the data transmission and coordination complexity increases
Solution Approach 1:
The management TB serves as an intermediary that coordinates between multiple sub-TBs. It receives simulation input signals from sub-TBs, manages the verification process, and collects simulation results, ensuring accurate data transmission and coordination across the parallel verification system
Solution Approach 2:
The management TB performs multiple functions including controlling sub-TBs to start verification, receiving simulation input signals, obtaining benchmark results, and verifying the chip based on collected data. This multi-functionality reduces the need for additional coordination mechanisms, maintaining data transmission accuracy while supporting parallel verification
3Speed
If separate transmission channels are implemented for different information types, then the data transmission efficiency is improved, but the system complexity increases
Solution Approach 1:
The communication infrastructure is segmented into distinct channels: control channels for management TB to sub-TBs, service channels for simulation input/output signals, and data channels for intermediate result transmission. This segmentation enables efficient, dedicated data transmission for each channel type while the management TB provides centralized coordination to manage the complexity
Data Source
AI summary
An example of the disclosure provides a chip verification system, a method, a device, apparatus and a storage medium, and relates to the technical field of chip verification. The system including a management TB and a simulation TB; the management TB is to control a head TB to start verification through a control channel; the head TB is to generate a simulation input signal and send the simulation input signal to the management TB through a service channel; each of the sub-TBs is to run a locally deployed sub-DUT file to obtain an intermediate result, and send the obtained intermediate result to other sub-TBs through a data channel; a tail TB is to obtain a simulation result for the service simulation task and send the simulation result to the management TB through a service channel; the management TB is further to obtain a benchmark result of the service simulation task based on the simulation input signal, and verify the chip according to the benchmark result and the simulation result. The scheme provided by the example of the disclosure can improve an efficiency of chip verification.