Parallel Sub-ADC Averaging for Adjustable Accuracy and Power
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in achieving enhanced and adjustable accuracy while minimizing power dissipation, as they are often designed for worst-case scenarios, leading to inefficient power usage and unpredictable performance in varying conditions.
Innovation Solution
The proposed solution involves an analog-to-digital converter comprising multiple sub-ADCs that operate in parallel, with a digital signal processing block to calculate the average output, allowing for adjustable performance by enabling or disabling sub-ADCs and using clock conditioning circuitry to distribute sampling times, thereby optimizing power dissipation and signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ADC is designed for worst-case scenarios to ensure reliability, then accuracy and performance are improved, but power dissipation increases significantly
Solution Approach 1:
The ADC is divided into multiple independent sub-ADCs that can be individually enabled or disabled. This segmentation allows the system to activate only the necessary number of sub-ADCs based on current performance requirements, rather than running all sub-ADCs at full power continuously. The digital signal processing block combines outputs from enabled sub-ADCs to achieve the required accuracy level.
Solution Approach 2:
The ADC system dynamically adjusts its operational mode by enabling or disabling sub-ADCs based on real-time performance requirements. The clock conditioning circuitry distributes sampling clocks selectively to enabled sub-ADCs, allowing the system to adapt power consumption to actual needs rather than operating statically at worst-case settings.
2Measurement precision
If accuracy is increased by using more sub-ADCs, then Signal-to-Noise Ratio is improved, but device complexity and power dissipation increase
Solution Approach 1:
The high-accuracy ADC is segmented into multiple parallel sub-ADCs with moderate individual accuracy. The digital signal processing block combines their outputs through averaging, which improves overall accuracy while keeping each individual sub-ADC simpler and less power-consuming than a single high-precision ADC would require.
Solution Approach 2:
Multiple sub-ADC outputs are merged in the digital signal processing block through averaging operations. This combining approach achieves higher effective accuracy and noise rejection without requiring each individual sub-ADC to be overly complex or power-intensive.
3Measurement precision
If accuracy is increased by increasing supply current, then measurement precision is improved, but power dissipation increases
Solution Approach 1:
Instead of increasing current in a single ADC, the system segments the conversion function across multiple sub-ADCs operating at lower currents. The combined output achieves the desired accuracy level while total power consumption is managed through selective enabling of sub-ADCs based on performance needs.
Solution Approach 2:
The system changes the operational parameters by adjusting which sub-ADCs are active rather than continuously varying supply current. This discrete parameter adjustment allows accurate control of power dissipation while maintaining required accuracy levels through the combination of enabled sub-ADCs.
Data Source
AI summary
An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.