Parallel Subblock Verify for NAND Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current storage devices, particularly in SLC mode, spend a significant portion of programming time on verify operations, which are inefficient due to the need to verify each page individually, limiting the number of pages that can be verified simultaneously and increasing system overhead.
Innovation Solution
Implementing a system that performs program verify operations on multiple subblocks in parallel, reducing the effective verify time by counting the number of bitlines that do not discharge in response to a verify read pulse, allowing for a probabilistic approach to verify operations without compromising quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If verify operations are performed on each page individually to ensure programming quality, then measurement precision is improved, but productivity deteriorates due to the sequential nature of verification
Solution Approach 1:
The memory device is divided into multiple subblocks, each with its own verify circuitry. This segmentation allows parallel verification of multiple subblocks simultaneously, transforming the sequential verify process into a parallel one, thereby improving programming speed while maintaining verification accuracy
Solution Approach 2:
Multiple verify operations that were previously performed sequentially on different pages are merged into a single simultaneous verify operation across multiple subblocks. The verify circuitry combines the verification of multiple subblocks in parallel, achieving both high productivity and measurement precision
2Productivity
If the number of pages verified simultaneously is increased to improve programming speed, then productivity is improved, but device complexity increases due to additional verify circuitry requirements
Solution Approach 1:
The verify circuitry is segmented into multiple independent verify units, each responsible for a specific subblock. This modular segmentation allows the system to scale verification capacity by adding more simple units rather than complicating a single verify circuit, improving productivity while managing device complexity
Solution Approach 2:
Each verify circuit unit is designed to be universal and can verify any subblock independently. This multi-functionality allows the same verify circuit design to be replicated across multiple subblocks, achieving parallel verification capability without proportionally increasing overall system complexity
3Reliability
If calibration is increased to maintain 100% non-sampling single loop for SLC programming, then reliability is improved, but loss of time increases due to extended verify operations
Solution Approach 1:
By segmenting the verification process across multiple subblocks that operate in parallel, the total verify time is reduced while maintaining the same calibration standards. Each subblock is verified independently and simultaneously, preserving reliability without the time penalty of sequential verification
Solution Approach 2:
The parallel verify operation allows multiple subblocks to be verified continuously and simultaneously rather than sequentially. This continuous parallel action maintains high calibration standards and reliability while eliminating the time loss associated with sequential verify operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves SLC programming time by approximately 30% without compromising quality, allowing for faster programming while maintaining reliable status reporting.
Implementation Method 1
counting a number of bitlines of the multiple subblocks that do not discharge in response to the verify read pulse
Data Source
AI summary
Program verify can be performed simultaneously on multiple subblocks in a storage device. The program verify occurs after a program operation of the storage cells. The program verify can include application of a verify read pulse to multiple subblocks simultaneously and then a count a number of bitlines of the multiple subblocks that do not discharge in response to the verify read pulse. The program verify passes if the count is within an expected range, instead of requiring all storage cells to pass program verify before moving on. If the number of bitlines not discharging is outside the expected range, the system can perform a second program pass.