Parallel Substitution Circuit Layout for Low-Power Encryption
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Solution Overview
Problem
Existing cryptographic operations in semiconductor memory devices are slow and consume high power, which is inefficient for secure data transmission in personalized electronic devices.
Innovation Solution
An encryption device with a substitution cluster circuit comprising different types of substitution circuits and a shift-row and mix-column circuit that perform arithmetic operations in parallel, reducing execution time and power consumption by optimizing gate count and propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic operations are implemented in hardware to improve security, then security is improved, but power consumption increases and execution time increases
Solution Approach 1:
The substitution circuit is divided into multiple substitution clusters, each containing different types of substitution circuits (first type with shorter execution time, second type with longer execution time). This segmentation allows the system to process data in parallel using different circuit types, optimizing both security and power consumption by selecting appropriate circuit types for different data segments.
Solution Approach 2:
Different substitution circuits within the substitution clusters have different execution time characteristics. The system uses first substitution circuits for data segments requiring faster processing and second substitution circuits for other segments, creating local quality variations that optimize overall performance while maintaining security requirements.
2Reliability
If cryptographic operations are implemented in hardware to improve security, then security is improved, but execution time increases
Solution Approach 1:
The substitution circuit is divided into multiple substitution clusters with different types of substitution circuits. This segmentation enables parallel processing of data segments through different circuit types, reducing overall execution time while maintaining the security requirements of cryptographic operations.
Solution Approach 2:
The system dynamically selects and uses different types of substitution circuits (first type with shorter execution time, second type with longer execution time) based on data segment requirements. This dynamic approach allows the system to optimize execution time by using faster circuits when possible while maintaining security through the use of more thorough circuits when needed.
3Manufacturing precision
If substitution circuits with longer execution time are used to improve substitution accuracy, then substitution accuracy is improved, but overall encryption speed decreases
Solution Approach 1:
The encryption data is divided into multiple segments that are processed by different substitution circuits simultaneously. First substitution circuits process some segments with shorter execution time while second substitution circuits process other segments with longer execution time, achieving both accuracy and speed through parallel segmented processing.
Solution Approach 2:
The system merges the outputs of multiple substitution circuits (both first type and second type) from parallel processing paths. By combining the results of substitutions performed with different execution times, the system achieves both high accuracy (from the second type circuits) and high speed (from the first type circuits and parallel processing).
Data Source
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AI summary
An encryption device (10) for performing a cryptographic operation on input data to generate output data, including: a substitution cluster circuit configured to perform a substitution operation on the input data, wherein the substitution cluster circuit includes first substitution circuits (S1) and second substitution circuits (S2); a shift-row and mix-column circuit configured to: receive a first substitution data set from the first substitution circuits (S1), receive a second substitution data set from the second substitution circuits (S2), and perform a shift-row operation and a mix-column operation on the first substitution data set and the second substitution data set to generate mixed data; and a round key addition circuit configured to perform a key addition operation on the mixed data to generate the output data, wherein an execution time of each first substitution circuit (S1)is shorter than an execution time of each second substitution circuit (S2).