Parallel Substrate Semiconductor Memory Device Design
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing size and manufacturing costs while maintaining high yield and design flexibility, particularly in stacked structures that are cost-effective and reliable.
Innovation Solution
The semiconductor memory device design incorporates a substrate with parallel row decoder and page buffer blocks, and bit and word lines, allowing for efficient use of space and separate manufacturing of memory cell arrays and peripheral blocks, which reduces the need for spare connection space and enhances design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the memory cell array and peripheral block are stacked vertically to decrease device size, then the area is reduced, but the manufacturing complexity and yield control become more difficult
Solution Approach 1:
The patent divides the semiconductor device into two separate substrates: a first substrate containing the memory cell array and a second substrate containing the peripheral block. This segmentation allows each substrate to be manufactured and tested independently, simplifying the manufacturing process while enabling vertical stacking to reduce overall device area. The separate substrates are subsequently bonded together to form the complete device.
2Ease of manufacture
If the device size is reduced to increase the number of devices per wafer, then manufacturing cost decreases, but the manufacturing precision and yield become more challenging
Solution Approach 1:
By segmenting the device into separate memory cell array and peripheral block substrates, each can be optimized and manufactured independently with appropriate precision requirements. This reduces the overall manufacturing precision demands compared to fabricating a fully integrated small device, thereby improving yield while maintaining cost benefits from reduced device size.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked architecture. By placing the memory cell array and peripheral block on separate substrates stacked vertically, the device achieves higher integration density without proportionally increasing manufacturing precision requirements, as each substrate can be manufactured separately with standard precision levels.
3Adaptability or versatility
If parallel structures are used for row decoder and page buffer blocks, then design flexibility improves, but the device complexity increases
Solution Approach 1:
The parallel structures of row decoder and page buffer blocks are implemented on the same second substrate, allowing independent design optimization while maintaining physical integration. This segmentation within the peripheral block substrate provides design flexibility for each functional unit while keeping the overall device complexity manageable through substrate-level integration.
Data Source
AI summary
A semiconductor memory device includes a substrate, first memory cells that are connected to first word lines extending along a first direction and first bit lines extending along a second direction, over the substrate, first conductive materials that are connected to the first word lines and extend from the first word lines along a third direction perpendicular to the first direction and the second direction, second conductive materials that are connected to the first bit lines and extend along the first direction over the first bit lines, and third conductive materials that are connected to the second conductive materials and extend from the second conductive materials along the third direction.