Parallel Sub-TFT ESD Circuit for Narrow-Bezel Display Panels
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Solution Overview
Problem
High-end display panels face issues with large parasitic capacitance load and signal delay due to numerous peripheral circuits, which hinder the implementation of narrow-bezel designs and affect display quality.
Innovation Solution
An ESD circuit with a first TFT and a second TFT, each comprising multiple sub-TFTs in parallel connection, enhances the W/L ratio and current load capacity while minimizing circuit area and capacitance, effectively managing electrostatic discharge through signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous peripheral circuits are disposed in the peripheral circuit region, then the ESD circuit can provide adequate protection, but large parasitic capacitance load is formed causing signal delay
Solution Approach 1:
The first TFT is divided into multiple first sub-TFTs connected in parallel, and the second TFT is divided into multiple second sub-TFTs connected in parallel. This segmentation increases the W/L ratio and current load capacity while maintaining compact circuit area, thereby providing adequate ESD protection without forming large parasitic capacitance load that causes signal delay.
2Reliability
If numerous peripheral circuits are disposed in the peripheral circuit region, then the ESD circuit can provide adequate protection, but the circuit area increases which is unfavorable for narrow-bezel implementation
Solution Approach 1:
Adjacent first sub-TFTs share common source electrodes or drain electrodes, and adjacent second sub-TFTs share common source electrodes or drain electrodes. This merging approach reduces the total number of electrodes and interconnections, thereby decreasing the overall circuit area while maintaining adequate ESD protection capability for narrow-bezel implementation.
Solution Approach 2:
The TFTs are segmented into multiple sub-TFTs in parallel configuration, which increases the effective W/L ratio and current handling capacity within a compact area, providing sufficient ESD protection without occupying excessive circuit area.
3Power
If the W/L ratio of the first TFT is increased to improve current load capacity, then the discharge capability is enhanced, but the circuit area increases
Solution Approach 1:
The first TFT is divided into multiple first sub-TFTs connected in parallel. This segmentation effectively increases the total W/L ratio and current load capacity without proportionally increasing the circuit area, as the sub-TFTs are arranged in a compact configuration with shared electrodes.
Solution Approach 2:
The sub-TFTs are arranged in a parallel configuration that utilizes both horizontal and vertical dimensions efficiently. This dimensional arrangement allows the circuit to achieve high current load capacity without linearly increasing the occupied area, thereby enhancing discharge capability while maintaining compact form factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ESD circuit improves the W/L ratio and current load capacity, reducing signal delay and nonuniformity, thus enhancing display quality and enabling narrow-bezel designs without increasing circuit size or capacitance.
Implementation Method 1
An ESD circuit with a first TFT and a second TFT, each comprising multiple sub-TFTs in parallel connection, enhances the W/L ratio and current load capacity while minimizing circuit area and capacitance, effectively managing electrostatic discharge through signal lines.
Data Source
Figure 1a~1b
Figure 1c~1d
Figure 1e~1f
AI summary
An electrostatic discharge (ESD) circuit, an array substrate and a display device are provided. The ESD circuit including a first signal line (10), a second signal line (20) and a first thin film transistor (TFT) (40), wherein the first TFT (40) includes a plurality of first sub-TFTs (04); each first sub-TFT (04) includes a first source electrode (041) and a first drain electrode (042); the first sub-TFTs (04) are sequentially arranged; adjacent first sub-TFTs (04) share one first source electrode (041) or first drain electrode (042); one of the first signal line (10) and the second signal line (20) is electrically connected with the first drain electrode (042) of each first sub-TFT (04); and the other is electrically connected with the first source electrode (041) of each first sub-TFT (40). The ESD circuit improves the width to length (W/L) ratio of a first TFT and improves the current load capacity in the case of discharge.