Parallel Semiconductor Switching Circuit for Gate Resonance Suppression
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Solution Overview
Problem
In power conversion apparatuses for hybrid and electric automobiles, parallel-connected semiconductor switching elements experience operational defects due to differences in switching timing, leading to unbalanced current distribution and potential resonance-induced erroneous turn-on operations.
Innovation Solution
The semiconductor device is configured with a control unit that sets the impedance on the gate path between semiconductor switching elements higher than the impedance on the source paths, reducing resonance currents and preventing erroneous turn-on operations by adjusting the impedance ratio to at least ten times higher on the gate line compared to the source lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If semiconductor switching elements are connected in parallel to increase power capacity, then power processing capability is improved, but switching timing differences cause current unbalance and operational defects
Solution Approach 1:
The patent changes the impedance parameter of the gate path by introducing a gate path impedance element (resistor or inductor) to increase the gate path impedance. This parameter change suppresses resonance current between parallel-connected semiconductor switching elements, preventing erroneous turn-on operations and improving operational reliability while maintaining high power capacity
Solution Approach 2:
The patent introduces an intermediary element (gate path impedance element) in the gate path between the gate drive circuit and the semiconductor switching elements. This intermediary suppresses the harmful resonance current by increasing the gate path impedance, thereby preventing current unbalance and operational defects in parallel-connected devices
2Reliability
If gate path impedance is increased to suppress resonance current, then operational defects are reduced, but gate drive efficiency may be affected
Solution Approach 1:
The patent carefully selects and adjusts the impedance value of the gate path impedance element to achieve an optimal balance. The impedance is increased sufficiently to suppress resonance current and prevent erroneous turn-on, but not so high as to excessively affect gate drive efficiency and switching speed
Solution Approach 2:
The patent applies impedance modification locally only in the gate path where resonance occurs, rather than uniformly across the entire circuit. This localized approach targets the specific problem area (gate path resonance) without unnecessarily affecting other parts of the circuit including the power handling paths
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces gate lift and inhibits operational defects in semiconductor switching elements, ensuring reliable operation even during high-speed switching, while maintaining a compact and efficient design.
Implementation Method 1
a gate path impedance element 10Lg, 10Ra inserted in the gate path 10 between the gate drive circuit 15 and the semiconductor switching elements 11
Implementation Method 2
differences in switching timing among the semiconductor switching elements 11 connected in parallel... occurrence of unbalance in current among the power modules... concentration of current in a power module turned on earliest
Data Source
AI summary
A semiconductor device includes: a first circuit including semiconductor switching elements connected in parallel, each semiconductor switching element having a first electrode, a second electrode, and a third electrode and being configured to be controlled, according to a voltage between the first electrode and the third electrode, to attain conduction or non-conduction between the second electrode and the third electrode; and a control unit connected to the first electrode of each semiconductor switching element and configured to control the voltage between the first electrode and the third electrode. The semiconductor device is configured to satisfy a first condition that an impedance Zg on a first path between the first electrodes of the respective semiconductor switching elements is higher, by at least a set value, than an impedance Zs on a third path making connection between the third electrodes of the respective semiconductor switching elements.