Parallel Symbol Decoding for HEVC Video Streams

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Solution Overview

Problem

High-resolution 4K and 8K Ultra-HD video decoding requires more efficient video compression standards due to higher bit rates, with existing serial decoding methods limiting performance in HEVC decoders.

Innovation Solution

Incorporating length fields into the binary symbol stream allows for parallel decoding of binary symbols, enabling the HEVC decoder to process multiple symbols simultaneously, thereby enhancing decoding efficiency for high-resolution video streams.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If serial decoding is used to handle variable-length binary symbols, then decoding accuracy is maintained, but decoding speed and productivity deteriorate

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoding speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The binary symbol stream is segmented into fixed-width chunks (e.g., 64 bits each) with inserted length fields that mark the boundaries of variable-length symbols. This segmentation allows the decoder to process multiple symbols in parallel while maintaining accurate symbol boundaries, resolving the contradiction between decoding accuracy and speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Length fields are inserted as intermediary elements within the binary symbol stream. These length fields act as markers that indicate the boundaries of variable-length symbols, enabling the parallel decoder to correctly identify and process each symbol without confusion, thus maintaining decoding accuracy while enabling parallel processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the decoder operates at very high frequency to maintain performance, then decoding speed is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improvedecoding performanceVSAvoiddecoder complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

By segmenting the binary stream into fixed-width chunks with embedded length fields, the decoder can use multiple parallel decoding paths operating at lower frequencies instead of a single high-frequency path, reducing device complexity while maintaining overall decoding performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-serial decoding dimension to a multi-parallel decoding dimension by processing multiple fixed-width binary chunks simultaneously. This dimensional change allows the system to achieve high throughput through parallelism rather than high frequency, reducing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If length fields are inserted into the binary symbol stream, then parallel decoding capability is improved, but device complexity increases

Engineering Contradiction:
Improveparallel processing capabilityVSAvoiddecoder structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The length information is extracted from the variable-length symbol structure and placed into separate fixed-width length fields. This extraction simplifies the overall decoding structure by separating the length indication function from the symbol data, making parallel processing easier to implement despite the added fields.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter representation by converting variable-length symbol encodings into fixed-width binary chunks with separate length field parameters. This parameter transformation enables parallel processing architectures while the added complexity is offset by the regularity and predictability of the new structure.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9432688B2Parallel symbol decoding
Publication Date: 2016.08.30 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9432688B2 patent drawing
  • US9432688B2 patent drawing
  • US9432688B2 patent drawing

AI summary

A device for parallel symbol decoding may include a first and second block. The first block is configured to convert a bitstream into a stream of binary symbols corresponding to motion vector data and other compressed image data, insert length fields into the stream of binary symbols that are each indicative of a number of consecutive binary symbols that correspond to motion vector data, and store the stream of binary symbols in a buffer. The second block is configured to retrieve the stream of binary symbols from the buffer, determine, based at least in part on the inserted length fields, consecutive binary symbols that correspond to motion vector data, decode the consecutive binary symbols that correspond to motion vector data via a first decode path, and to decode binary symbols that correspond to other compressed image data via a second decode path that is independent of the first decode path.