Error-Correction Coding for Parallel Multilevel Symbol Frames
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed optical transmission systems face inefficiencies in error correction coding due to increased circuit scale and latency, particularly when using block-coding schemes for multilevel modulation symbols, which require multiple coding circuits and frame adjustment memories.
Innovation Solution
An error correction coding apparatus that treats known bits as information bits for parallel processing, replacing them with parity bits generated during the coding process, allowing for low-latency error correction without increasing circuit scale by using a single error correction coding circuit for multiple bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If block-coding is performed for each bit sequence of multilevel modulation symbols in parallel, then processing speed is improved, but circuit scale increases due to requiring multiple coding circuits
Solution Approach 1:
The bit sequence is divided into multiple parallel channels, each processed by a separate coding circuit. This segmentation enables simultaneous processing of multiple bit sequences, achieving parallel processing speed improvement while keeping each individual coding circuit relatively simple in scale.
2Reliability
If block-coding is performed for each bit sequence of multilevel modulation symbols, then error correction performance is improved, but circuit scale increases due to requiring multiple coding circuits
Solution Approach 1:
The error correction function is segmented across multiple parallel coding circuits, each handling a specific bit sequence. This allows the system to achieve comprehensive error correction performance for all bit sequences while distributing the circuit complexity across multiple simpler units rather than requiring one large complex circuit.
3Device complexity
If sequential coding is used for multilevel modulation symbols, then circuit scale is reduced, but processing latency increases
Solution Approach 1:
The processing is segmented into multiple parallel channels that operate simultaneously. Each channel processes a different bit sequence through its own coding circuit, eliminating the sequential waiting time and reducing overall processing latency while keeping each individual circuit segment manageable in scale.
4Reliability
If frame adjustment memories are added for probabilistic signal shaping, then error correction performance is improved, but circuit scale increases
Solution Approach 1:
The frame adjustment memory function is merged with the existing coding circuit structure. Rather than adding separate memory components, the patent integrates the shaping functionality into the coding process itself, achieving improved error correction performance while avoiding additional circuit scale increase from separate memory units.
Data Source
Figure 1(a)~1(b)
Figure 2
Figure 3
AI summary
An error correction coding apparatus (100A) that performs error correction coding using, as an error correction code sequence, a frame of m bits × n symbols input in m-bit parallel, where m and n are positive integers, includes: an error correction coding circuit (2) that performs error correction coding using, as information bits, m bits × n symbols including known bits assigned to a bit sequence specified in the error correction code sequence and generate error correction coded parity bits; and a selector (4) that replaces the known bits of the error correction code sequence with the parity bits.