Parallel Symbol-to-Wire Encoding for Higher C-PHY Throughput
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Solution Overview
Problem
Existing communication protocols like MIPI C-PHY require sequential conversion of symbols into wire states, limiting data rates due to hardware limitations at high clock speeds, which can be overcome by converting symbols into wire states in parallel.
Innovation Solution
A transmitter system that includes a symbol mapper and encoder configured to convert multiple symbols into respective wire states in parallel, using the current and previous symbols to determine wire states, allowing for slower clock speeds while maintaining high data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential conversion of symbols into wire states is used, then hardware can operate at lower clock speeds, but data rate is limited
Solution Approach 1:
The patent segments the symbol encoding process into independent parallel operations by pre-computing transition tables for each possible symbol value. Each symbol encoder can independently lookup its wire state using the transition table, eliminating sequential dependencies and enabling parallel processing of multiple symbols simultaneously.
Solution Approach 2:
The patent performs preliminary action by pre-computing and storing transition tables that define the relationship between symbols and wire states. This pre-computation is done offline or during system initialization, allowing the actual encoding process to simply perform table lookups, significantly reducing the computational complexity during real-time operation.
2Productivity
If parallel conversion of symbols into wire states is implemented, then data rate increases, but hardware complexity increases
Solution Approach 1:
The patent uses copying by creating multiple identical symbol encoder units, each with its own transition table lookup logic. These encoder units can process different symbols in parallel simultaneously. By copying the encoder architecture rather than creating a complex sequential processor, the system achieves parallelism with relatively simple replicated hardware blocks.
3Productivity
If high clock speeds are used for sequential conversion, then data rate increases, but hardware reliability decreases
Solution Approach 1:
The patent replaces the mechanical sequential processing system with a lookup-based combinatorial logic system. Instead of using a sequential state machine that updates wire states one at a time based on previous states, the system uses parallel lookup tables that directly map symbol values to wire states, eliminating the need for high-speed sequential operations and associated timing constraints.
Data Source
AI summary
Embodiments herein describe techniques for converting multiple symbols into respective wire states in parallel. In one embodiment, the techniques can be used to convert symbols into wire states in parallel even when those wire states are dependent on previously determined wire states. That is, the dependency on previous wire states can be removed so that wire states can be determined in parallel.