Parallel Synchronizer Cells for Metastability-Resilient Clock Crossing
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Solution Overview
Problem
Digital integrated circuits face challenges in synchronizing asynchronous clock domains, leading to metastability issues that cause data corruption and system failures, particularly exacerbated by reduced power supply voltage and increasing clock speeds.
Innovation Solution
The implementation of synchronization circuits that operate at reduced clock frequencies, using serial or parallel configurations of flip-flops, with clock signals divided by a factor of N, providing additional time for metastability resolution and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronization devices operate at high clock frequencies, then productivity is improved, but reliability deteriorates due to increased metastability probability
Solution Approach 1:
The synchronization circuit is divided into multiple parallel synchronization devices (first, second, and third synchronization devices) that operate at different clock frequencies. The first device operates at a lower frequency while the second and third devices operate at higher frequencies, allowing the system to segment the synchronization function across multiple operational modes to maintain reliability while achieving high productivity.
Solution Approach 2:
The patent introduces a frequency dimension by operating synchronization devices at different clock frequencies simultaneously. The first synchronization device operates at a first clock frequency while the second and third devices operate at a second clock frequency that is higher than the first, adding frequency as a dimensional variable to resolve the contradiction between speed and reliability.
2Reliability
If clock frequency is reduced to resolve metastability, then reliability is improved, but productivity deteriorates
Solution Approach 1:
The synchronization function is segmented across multiple devices operating in parallel at different frequencies. The first synchronization device operates at a lower frequency to reliably resolve metastability, while the second and third devices operate at higher frequencies to maintain data transfer speed, with logic circuitry combining their outputs to achieve both reliability and productivity.
Solution Approach 2:
The patent merges the outputs of multiple synchronization devices operating at different frequencies through logic circuitry. The second logic circuit receives inputs from both the first and second synchronization devices and generates an output that combines the benefits of both operational modes, achieving reliable metastability resolution while maintaining high data transfer speed.
3Use of energy by moving object
If power supply voltage is reduced, then energy efficiency is improved, but reliability deteriorates due to degraded metastability resolution
Solution Approach 1:
The patent changes the clock frequency parameter of synchronization devices to compensate for reduced power supply voltage. By operating the first synchronization device at a lower frequency and the second and third devices at higher frequencies, the system maintains reliable metastability resolution even when power supply voltage is reduced for energy efficiency.
Data Source
AI summary
In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization circuit. In at least one embodiment of the invention, a method includes sampling a first signal at a first frequency to thereby generate a plurality of sampled versions of the first signal. The first frequency is a frequency of a clock signal divided by N. N is a number greater than one. The method includes sampling a second signal at the frequency of the clock signal. The second signal is based on sequentially selected ones of the plurality of sampled versions of the first signal to thereby generate an output version of the first signal.