Parallel Synchronizer Circuit for Soft Error Tolerance
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Solution Overview
Problem
As device geometries shrink, synchronizer flip-flops become more susceptible to soft errors caused by cosmic radiation, power supply noise, or other external events, leading to faults in digital systems, especially in safety-critical applications.
Innovation Solution
A synchronizer circuit that detects and compensates for soft errors by employing two parallel synchronizers and selection circuitry to ensure that the output changes state only after any soft errors are resolved, thereby reducing or eliminating errors caused by soft errors in synchronizer flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometries are shrunk to increase integration density, then productivity and device density are improved, but synchronizer flip-flops become more susceptible to soft errors from cosmic radiation and power supply noise
Solution Approach 1:
The synchronizer is divided into multiple independent flip-flops (first flip-flop, second flip-flop, third flip-flop) that operate in parallel. Each flip-flop processes the asynchronous signal independently, and their outputs are combined through selection circuitry. This segmentation allows the system to maintain high density while improving reliability through redundancy.
Solution Approach 2:
The circuit incorporates selection circuitry and feedback mechanisms that detect soft errors before they propagate to the output. When a soft error is detected in any flip-flop, the selection circuitry switches to alternative flip-flops or holds the previous valid state, cushioning against the harmful effects of soft errors before they can affect system operation.
2Device complexity
If traditional single flip-flop synchronizers are used, then device complexity is low, but soft errors cause faults in digital systems
Solution Approach 1:
The synchronizer is divided into multiple independent flip-flops (first flip-flop, second flip-flop, third flip-flop) that operate in parallel. Each flip-flop processes the asynchronous signal independently, and their outputs are combined through selection circuitry. This segmentation allows the system to maintain high density while improving reliability through redundancy.
Solution Approach 2:
The circuit uses feedback connections where the output of each flip-flop is fed back to the selection circuitry. The selection circuitry continuously monitors the outputs and adjusts its selection based on the current state, creating a feedback mechanism that detects and compensates for soft errors by switching to valid states when errors occur.
3Reliability
If parallel synchronizers with selection circuitry are implemented, then soft error tolerance is improved, but device complexity increases
Solution Approach 1:
The synchronizer is divided into multiple independent flip-flops (first flip-flop, second flip-flop, third flip-flop) that operate in parallel. Each flip-flop processes the asynchronous signal independently, and their outputs are combined through selection circuitry. This segmentation allows the system to maintain high density while improving reliability through redundancy.
Solution Approach 2:
The synchronizer circuit is self-diagnosing and self-correcting. The selection circuitry automatically detects soft errors by monitoring flip-flop outputs and autonomously switches to alternative flip-flops or holds previous valid states without external intervention. This self-service capability improves reliability while minimizing the need for additional control logic.
Data Source
AI summary
A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.