Parallel Syndrome Generation for Low-Latency Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As communication speed and data throughput increase, error correction latency in error correction decoders lengthens due to the rising number of error bits in information data, necessitating a solution to reduce this latency.
Innovation Solution
An error correction device and method that generate partial coefficients in parallel with syndromes for the error location equation, utilizing a syndrome generation circuit, partial coefficient generation circuit, error location determination circuit, and error correction circuit to determine and correct errors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If error correction decoding is performed sequentially (syndrome generation first, then coefficient generation), then the decoding process is simple to implement, but error correction latency increases
Solution Approach 1:
The patent applies preliminary action by generating partial coefficient information in advance during the syndrome generation phase. Specifically, the coefficient generation circuit starts generating partial coefficients (such as S1³, S1²S3, etc.) while the syndrome generation circuit is still computing the syndromes. This overlapping of operations allows the error location polynomial coefficients to be ready sooner, reducing the overall error correction latency without requiring a completely complex rearchitecture of the decoding process
Solution Approach 2:
The patent introduces a temporal dimension to the decoding process by organizing operations into overlapping time windows. Instead of strict sequential execution (Phase 1: Syndrome generation, Phase 2: Coefficient generation), the system allows coefficient generation to start in the latter part of syndrome generation and complete in the former part of error location determination. This dimensional reorganization of the decoding timeline enables parallel execution of previously sequential tasks, reducing total latency while maintaining implementation feasibility
2Productivity
If parallel generation of syndromes and partial coefficients is implemented, then error correction latency is reduced, but device complexity increases
Solution Approach 1:
The patent segments the coefficient generation task into partial coefficient generation (during syndrome generation) and complete coefficient assembly (after syndrome generation). The coefficient generation circuit is divided into multiple sub-circuits that compute different partial coefficients in parallel (e.g., one sub-circuit computes S1³, another computes S1²S3, etc.). This segmentation allows the system to achieve parallel processing benefits while keeping each individual circuit module relatively simple, thus improving productivity without excessive increase in overall device complexity
Solution Approach 2:
The coefficient generation circuit is designed with multi-functionality to perform both partial coefficient generation during the syndrome generation phase and complete coefficient assembly afterward. The same circuit resources are reused for different purposes at different times, reducing the need for dedicated separate circuits for each function. This universal design improves data processing speed through parallel operation while controlling device complexity by avoiding redundant circuitry
Data Source
AI summary
An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.