Parallel Time-to-Digital Converter Circuitry for High-Resolution Phase Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing time-to-digital converters face challenges with maximum resolution, range, power consumption, implementation complexity, accuracy, noise, and non-linearity that are higher than desired.
Innovation Solution
A time-to-digital converter circuitry with a plurality of constituent TDCs that operate in parallel, serial, or intermediate modes, utilizing stochastically generated and randomly distributed delays for reference signals, and a digital signal combiner to produce a digitally represented output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional TDC architecture is used, then implementation is simpler, but resolution is lower than desired
Solution Approach 1:
The TDC is divided into multiple independent TDC cells, each contributing to the overall resolution. By segmenting the conversion function across multiple cells with different delay ranges, the patent achieves high resolution without requiring a single complex circuit, thereby resolving the contradiction between resolution and implementation complexity.
Solution Approach 2:
The patent transitions from a single-dimensional delay measurement to a multi-dimensional approach by combining coarse delay (from delay line selection) and fine delay (from TDC cell measurement). This dimensional expansion allows achieving high resolution through coordinate-like combination rather than requiring extremely fine single-dimensional grading, reducing overall system complexity.
2Loss of time
If delay line length is increased to extend measurement range, then range is improved, but non-linearity and noise increase
Solution Approach 1:
The measurement range is segmented into multiple delay lines, each optimized for a specific time range with appropriate delay increments. By selecting the appropriate delay line based on the input signal timing, the system achieves extended overall range while maintaining low non-linearity within each segment, avoiding the need for a single long delay line that would introduce excessive non-linearity.
Solution Approach 2:
The patent dynamically changes the delay line selection parameter based on the measured time range. By switching between different delay lines with different delay characteristics, the system adapts to extend measurement range while maintaining optimal non-linearity performance for each range, thereby resolving the contradiction between range extension and non-linearity control.
3Measurement precision
If more TDC cells are added to increase resolution, then resolution is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic selection of active TDC cells based on the measured time range. Not all TDC cells are activated simultaneously; instead, the system dynamically enables only the necessary cells for the current measurement task. This dynamic operation reduces average power consumption while maintaining high resolution capability when needed, resolving the contradiction between resolution and power consumption.
Solution Approach 2:
The system changes operational parameters by adjusting which TDC cells are active based on measurement requirements. By dynamically modifying the active cell configuration, the patent achieves high resolution only when necessary while reducing power consumption during normal operation, thereby balancing resolution and power consumption.
4Measurement precision
If Vernier delay structure is used to achieve high resolution, then resolution is improved, but device size and complexity increase
Solution Approach 1:
Instead of using a single complex Vernier delay structure, the patent segments the delay measurement into multiple independent TDC cells, each with simpler delay structures. This segmentation achieves equivalent or superior resolution through coordinated operation of multiple simple cells, avoiding the large device size and complexity of a monolithic Vernier structure.
Solution Approach 2:
The patent merges the functionality of multiple simple TDC cells to achieve the resolution capability traditionally requiring a complex Vernier structure. By combining the measurement results from multiple cells with different delay characteristics, the system achieves high resolution with smaller individual components, thereby reducing overall device size and complexity compared to a single Vernier implementation.
Data Source
Figure 1~2
Figure 3
Figure 4~8
AI summary
A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal (109) and an input clock signal (110) to a digitally represented output signal (139). The TDC circuitry comprises a plurality of constituent TDC:s (101, 102, 103), a reference signal provider (120), and a digital signal combiner (130). Each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183) and a constituent clock signal (110) to a digitally represented constituent output signal (131, 132, 133). The reference signal provider (120) is configured to provide the respective constituent reference signals (181, 182, 183) to each of the constituent TDC:s (101, 102, 103). In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal (109) with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner (130) is configured to provide the digitally represented output signal (139) based on the digitally represented constituent output signals (131, 132, 133) of the constituent TDC:s. A corresponding method and devices comprising the TDC circuitry are also disclosed.