Parallel Time-to-Digital Converter for Higher Resolution and Linearity

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Solution Overview

Problem

Existing time-to-digital converters face limitations in resolution, range, power consumption, implementation complexity, accuracy, noise, and non-linearity, which hinder their performance in achieving high-resolution time-to-digital conversion.

Innovation Solution

A time-to-digital converter circuitry comprising multiple constituent TDCs with stochastically generated and randomly distributed delays, operating in parallel or serial modes, and a digital signal combiner to produce a digitally represented output signal, allowing for flexible operation and improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional TDC architectures are used, then the circuit implementation is simpler, but the resolution is lower than desired

Engineering Contradiction:
ImproveresolutionVSAvoidimplementation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The TDC is divided into multiple independent constituent TDCs, each processing a portion of the time interval. This segmentation allows parallel processing of time measurements, achieving high resolution through the combination of multiple coarse measurements rather than requiring a single complex fine-resolution TDC.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from temporal sequencing to spatial parallelism by operating multiple constituent TDCs simultaneously. Instead of using a single TDC that sequentially processes time intervals, multiple TDCs measure different aspects of the time difference in parallel, converting a time-domain problem into a space-domain solution.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If conventional TDC architectures are used, then the circuit size is smaller, but the maximum time range is lower than desired

Engineering Contradiction:
Improvemaximum time rangeVSAvoidcircuit size
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The total time measurement range is segmented across multiple constituent TDCs, each capable of measuring a limited time interval. By combining the outputs of these segmented TDCs, the system achieves a total measurement range that exceeds what any single TDC could provide, effectively extending the range without proportionally increasing the area of each individual TDC.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple constituent TDCs are merged in parallel to form a composite TDC system. The individual TDCs work together to cover a broader time range, with each contributing a portion of the total measurement capability. This merging allows the system to achieve extended range while keeping individual TDC units compact.

Inventive Principle:
Principle #5Merging (Combining)

3Object-affected harmful factors

If conventional TDC architectures are used, then the power consumption is acceptable, but the noise is higher than desired

Engineering Contradiction:
ImprovenoiseVSAvoidpower consumption
Core Design Contradiction:
Object-affected harmful factorsVSUse of energy by moving object

Solution Approach 1:

The noise from individual constituent TDCs is segmented and distributed across multiple channels. By measuring the time difference through multiple independent paths and combining the results, random noise components tend to average out, reducing the overall noise impact on the measurement accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent exploits random variations and noise characteristics by using stochastically generated delay values. Instead of treating random variations as harmful, the system uses them to create a distributed measurement approach where the statistical properties of the noise can be averaged out, converting what would normally be a detrimental factor into a mechanism that enables noise reduction through statistical averaging.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

4Measurement precision

If conventional TDC architectures are used, then the non-linearity is higher than desired, but the implementation is more straightforward

Engineering Contradiction:
ImproveaccuracyVSAvoidimplementation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The non-linearity of individual constituent TDCs is segmented and distributed across multiple units. By combining measurements from multiple TDCs with different characteristic curves, the overall system achieves improved linearity as the individual non-linearities tend to cancel each other out through statistical averaging.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent converts the harmful effect of individual TDC non-linearities into a beneficial outcome by using random variations in delay characteristics. The non-linear behavior of each constituent TDC, when combined with others having different non-linear characteristics, results in an overall linearized system through statistical averaging, turning a source of error into a linearity improvement mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11868094B2Time-to-digital converter circuitry
Publication Date: 2024.01.09 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US11868094B2 patent drawing
  • US11868094B2 patent drawing

AI summary

A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal (109) and an input clock signal (110) to a digitally represented output signal (139). The TDC circuitry comprises a plurality of constituent TDC:s (101, 102, 103), a reference signal provider (120), and a digital signal combiner (130). Each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183) and a constituent clock signal (110) to a digitally represented constituent output signal (131, 132, 133). The reference signal provider (120) is configured to provide the respective constituent reference signals (181, 182, 183) to each of the constituent TDC:s (101, 102, 103). In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal (109) with different respective delays for at least two of the respective constituent reference signals. The digital signal combiner (130) is configured to provide the digitally represented output signal (139) based on the digitally represented constituent output signals (131, 132, 133) of the constituent TDC:s. A corresponding method and devices comprising the TDC circuitry are also disclosed.