Parallel Tessellation Scheduling for Ordered Geometry Output
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Solution Overview
Problem
Graphics processing systems face increased latency and memory requirements due to the need to maintain the order of patch submission in tessellation, especially when patches vary significantly in processing time, leading to serialization and potential stalling of tessellation units.
Innovation Solution
A tessellation module with multiple cores and pipelines that break down tessellation work into smaller instances, allowing parallel processing without maintaining strict order, using a scheduler to distribute these instances across pipelines while ensuring correct output ordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If patches are processed in parallel to increase throughput, then productivity is improved, but latency increases due to ordering requirements
Solution Approach 1:
The patent segments the tessellation work into discrete patches that can be independently processed in parallel. Each patch is treated as a separate unit that can be submitted to and processed by different tessellation units simultaneously, enabling parallel throughput while maintaining ordering through the buffer mechanism.
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the parallel tessellation units and the output. This buffer temporarily stores primitives from different patches, allowing tessellation units to process patches in parallel while ensuring primitives are emitted in the correct order based on patch submission sequence, thus resolving the latency issue.
2Reliability
If memory buffer size is increased to prevent stalling, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a buffer of moderate size that is sufficient to handle typical variations in patch processing times without being excessively large. This partial buffering approach prevents stalling in most cases while avoiding the complexity and resource overhead of oversized buffers, striking a practical balance between reliability and complexity.
3Manufacturing precision
If patches are serialized to maintain order, then ordering accuracy is improved, but productivity decreases
Solution Approach 1:
The patent segments the processing into independent patch units that can be handled separately. By segmenting the work into discrete patches with clear identification, the system can process them in parallel while using the buffer to ensure correct ordering is maintained, avoiding full serialization.
Solution Approach 2:
The buffer acts as an intermediary that decouples the parallel processing from the sequential output requirement. It allows multiple patches to be processed simultaneously by different units while ensuring primitives are emitted in the correct order, thus maintaining precision without sacrificing productivity.
Data Source
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AI summary
A tessellation module configured to tessellate a patch to generate tessellated geometry data representing the tessellated patch, the tessellation module comprising: a plurality of cores, each core comprising a plurality of tessellation pipelines arranged to operate in parallel and a controller; and a patch distributor configured to replicate a set of patches and pass the set of patches to each of the plurality of cores; wherein each of the cores is configured to: process a respective patch of the set at a respective tessellation pipeline to identify tessellation factors for the patches of the set; determine, at the controller of the core, based on the identified tessellation factors for the patches of the set, tessellation instances to be used in tessellating the patches of the set, wherein each of the tessellation instances, determined for a patch, is associated with a portion of tessellated geometry that will be generated when the patch is tessellated so that the tessellated geometry associated with all of the tessellation instances for the patch collectively define the tessellated geometry data for the patch; determine, at the controller of the core, an allocation of the tessellation instances amongst the tessellation pipelines of the core; and process the tessellation instances at the allocated tessellation pipelines to generate tessellated geometry data associated with the respective allocated tessellation instances, wherein the controllers of the plurality of cores are configured such that a subset of the tessellation instances for a patch are allocated to the tessellation pipelines of a core, and such that collectively, over all of the cores, all of the tessellation instances for the patch are processed.