Parallel Test Circuit for Semiconductor Memory Sub-Banks
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Solution Overview
Problem
Conventional semiconductor memory apparatus testing at the package level is inefficient due to the need for sequential testing of memory cells through input/output pads, leading to prolonged test times and increased costs.
Innovation Solution
A parallel test circuit and method that utilize test global lines to simultaneously read data from multiple sub-banks, comparing data loaded in global lines to data on test global lines, generating a compression signal to determine memory cell integrity, and outputting a test signal to an input/output pad, allowing for simultaneous testing of multiple sub-banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential testing through input/output pads is used at package level, then testing can be performed with existing infrastructure, but test time is prolonged and productivity is reduced
Solution Approach 1:
The patent divides the memory bank into multiple sub-banks (first sub bank and second sub bank), each with dedicated test global lines. This segmentation allows parallel testing of multiple sub-banks simultaneously, transforming the sequential testing process into a parallel one, thereby significantly reducing test time and improving productivity.
Solution Approach 2:
The patent introduces test global lines as intermediary pathways that connect sub-banks to test pads. These test global lines enable direct access to sub-bank data during testing, bypassing the need for sequential access through the global line and input/output pads, thus accelerating the testing process.
2Device complexity
If multiple sub-banks share a global line, then device complexity is reduced, but testing must be performed sequentially increasing test time
Solution Approach 1:
The patent segments the testing infrastructure by providing dedicated test global lines for each sub bank. This segmentation allows simultaneous testing operations across multiple sub-banks without requiring complex arbitration or switching mechanisms, maintaining relatively simple device architecture while enabling parallel testing.
Solution Approach 2:
The test global lines serve multiple functions: they can be used for normal data transmission during operation and for dedicated testing during test mode. This multi-functionality reduces the need for separate dedicated test infrastructure, keeping device complexity low while enabling parallel testing capabilities.
Data Source
AI summary
A parallel test circuit of a semiconductor memory apparatus includes a memory bank which includes first and second sub banks having test global lines, respectively, and sharing a global line connected to each of the first and second sub banks. When a read command is applied during a test mode, the parallel test circuit compares data loaded in the global line to data loaded in the test global line of the second sub bank to attain a comparison result, compresses the comparison result to attain a compression signal, and outputs the compression signal as a test output signal to a pad.