Parallel Test Device I/O Line Compression
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Solution Overview
Problem
Conventional parallel test devices are unable to recognize defective parts in peripheral circuits during normal operation, leading to increased costs and failures in multi-chip packages due to undetected defects, as they rely on I/O line data compression and cannot effectively utilize unused I/O lines for testing.
Innovation Solution
A parallel test device and method that includes a pad unit for data I/O operations, input buffers for activating write data, output drivers for read data, and a test controller to manage signals during a test mode, allowing read data to be used as write data and enabling the compression of data for determining defective parts across all global I/O lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If I/O line data compression is used to test multiple chips with fewer I/O lines, then the number of I/O lines needed is reduced, but defective parts in peripheral circuits cannot be recognized
Solution Approach 1:
The patent divides the testing process into two distinct modes: compression test mode for high-speed parallel testing of memory cells, and normal test mode for comprehensive testing of peripheral circuits. This segmentation allows each mode to optimize for its specific purpose without compromising the other.
Solution Approach 2:
The patent implements dynamic switching between compression test mode and normal test mode based on testing requirements. The test controller can flexibly transition between modes, enabling the system to adapt its I/O line usage strategy according to the specific testing phase and defect detection needs.
2Productivity
If compression test mode is used to reduce testing time, then productivity increases, but defective parts in unused I/O lines and peripheral circuits remain undetected
Solution Approach 1:
The patent performs preliminary compression testing to quickly identify obviously defective chips, then follows up with normal mode testing on chips that pass the initial screening. This preliminary action approach maintains high productivity while ensuring comprehensive defect detection through subsequent detailed testing.
Solution Approach 2:
The patent ensures continuous testing coverage by maintaining the ability to switch between compression and normal modes without interrupting the testing workflow. The system continuously adapts its testing strategy, maintaining useful action throughout the entire testing process rather than having idle periods or incomplete testing.
3Device complexity
If a small number of I/O lines are used for parallel testing, then device complexity is reduced, but the ability to test all global I/O lines is compromised
Solution Approach 1:
The patent makes the I/O lines universal by enabling them to serve dual purposes: functioning as both compression test lines for parallel memory cell testing and normal test lines for comprehensive peripheral circuit testing. This multi-functionality eliminates the need for separate dedicated test lines for different testing purposes.
Solution Approach 2:
The patent implements dynamic reconfiguration of I/O line functionality, allowing the same physical I/O lines to be dynamically assigned to different testing functions based on the current test mode. This dynamic adaptation enables full I/O line coverage without requiring additional dedicated test infrastructure.
Data Source
AI summary
A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (I/O) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (GIO) line; a plurality of output drivers configured to activate read data received from the global I/O (GIO) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data.