Parallel Test Device I/O Pad Segmentation for Failure Detection
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Solution Overview
Problem
Current parallel test devices for memory devices, such as DRAM and NAND, face challenges in detecting failures due to the limitations of using a single I/O line for data compression, which results in degraded performance and inability to identify failed parts, especially with minor failures and critical data valid windows.
Innovation Solution
A parallel test device is designed with an I/O pad, multiple input buffers, and output drivers, which receives a test signal from an external device during a test mode, allowing for enhanced failure detection by utilizing a compression circuit and calibration device to compress and read/write data, and stress unused pads to identify failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single I/O line is used for data compression during testing, then the test device can handle large numbers of memory devices, but it becomes impossible to determine failed parts in the memory device
Solution Approach 1:
The patent divides the I/O interface into multiple independent I/O lines (first I/O line and second I/O line), each capable of independent data transmission. This segmentation allows the test device to simultaneously perform data compression and failure detection without interference, resolving the contradiction between test capacity and failure detection capability.
2Productivity
If an internal test controller is employed to address data written into multiple I/O lines using a single I/O line, then data compression is achieved, but the data setup/hold time becomes smaller than the data valid window causing performance degradation
Solution Approach 1:
The patent extracts the data compression function from the internal test controller and implements it externally using a separate compression circuit connected to the first I/O line. This extraction eliminates the timing conflict between data setup/hold time and data valid window, as the compression operation no longer competes for the same time resources as the data transmission through the second I/O line.
3Ease of operation
If unused parts including I/O buffer are active during testing, then the parallel test device can operate, but performance degrades even with minor failures in the memory device
Solution Approach 1:
The patent implements dynamic control of I/O buffers through enable signals that can selectively activate or deactivate specific I/O lines based on testing requirements. During failure detection phases, only the necessary I/O lines are activated while others are disabled, preventing performance degradation from unused components while maintaining operational flexibility.
Data Source
AI summary
A parallel test device is provided. The parallel test device of the disclosure includes an I/O pad, a plurality of input buffers, and a plurality of output drivers. The I/O pad is configured to perform input/output operations in the parallel test device. The input buffers are configured to enable write data. The output drivers are configured to enable read data and output the read data to the I/O pad. A test signal corresponds to the data from an external device is transferred to the output drivers through the I/O pad in the parallel test device during a test mode.