Parallel Test Key Architecture for Semiconductor Wafer Defect Detection
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Solution Overview
Problem
Current wafer-level testing methods for semiconductor wafers are slow and inaccurate due to the limited number of MOS transistors per test line, which hampers the detection of defects like voids and defects between fin-like gate terminals in MOS transistors.
Innovation Solution
Implementing a test line with a plurality of test keys connected in parallel, where each test key comprises multiple MOS transistors connected in series, allowing for a larger number of MOS transistors to be tested simultaneously by monitoring drain current drops in linear and saturation regions to enhance detectability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of MOS transistors per test line is limited (conventional approach), then the test line structure remains simple, but the testing speed becomes slow and accuracy is limited
Solution Approach 1:
The test line is segmented into multiple test keys, with each test key containing a series of MOS transistors. This segmentation allows the system to handle and test a larger number of transistors systematically, improving testing speed and accuracy without creating an unmanageably complex structure. The patent divides the test line into test keys TK1 to TKn, where each test key contains multiple MOS transistors arranged in series.
Solution Approach 2:
The patent transitions from a single-series test line configuration to a parallel configuration of multiple test keys. By arranging test keys in parallel and MOS transistors in series within each test key, the system adds a dimensional aspect to the test line structure, enabling simultaneous testing of multiple transistor sequences and significantly improving testing throughput.
2Measurement precision
If few MOS transistors are used per test line, then the test line configuration remains simple, but defect detection accuracy is limited
Solution Approach 1:
By segmenting the test line into multiple test keys with series-connected MOS transistors, the system can detect defects with higher precision. The series configuration within each test key allows for more accurate measurement of transistor characteristics, while the parallel arrangement of test keys provides multiple measurement opportunities, thereby improving overall defect detection accuracy.
Solution Approach 2:
The patent implements a testing mechanism that measures and compares electrical characteristics (such as threshold voltage and drain current) of MOS transistors across multiple test keys. This feedback approach allows for statistical analysis and comparison, enhancing defect detection accuracy by identifying anomalies that stand out against the backdrop of multiple measurements.
3Speed
If the gate terminal and drain terminal of MOS transistors are electrically connected, then the test line structure is simplified, but the testing speed becomes slow
Solution Approach 1:
The patent introduces a parallel dimension to the test line by creating multiple test keys connected in parallel. This dimensional change allows the system to test multiple MOS transistor sequences simultaneously, dramatically increasing testing speed. Each test key maintains its own series configuration of MOS transistors, preserving structural simplicity while achieving high-speed testing through parallel operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the number of MOS transistors tested per wafer, resulting in faster testing speeds and improved accuracy, with the testing speed being 420 times faster and detectability 1260 times higher than conventional methods.
Implementation Method 1
measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in each of the test keys
Data Source
AI summary
A method, a test line and a system for detecting defects on a semiconductor wafer are presented. The method includes measuring a current-voltage (IV) curve of a plurality of metal oxide semiconductor (MOS) transistors which are connected in series in a test key; comparing the measured IV curve with a reference curve to obtain a first drain current drop in a linear region and a second drain current drop in a saturation region; and determining whether at least one of the MOS transistor among the MOS transistors of the test key is defected according to at least one of the first drain current drop and the second drain current drop.