Parallel Test Pattern Input for Semiconductor DUT Testing

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Solution Overview

Problem

Current testing methods for semiconductor devices require sequential input and execution of test patterns, leading to time-consuming processes and inefficient generation of Shmoo plots.

Innovation Solution

A method and apparatus that allow multiple test patterns to be input simultaneously and performed automatically on a device under test without interruption, using a system comprising a testing device, controlling device, and computing device with non-transitory computer-readable media storing executable instructions to input, perform, and obtain results for each test pattern.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If multiple test patterns are input sequentially one at a time, then the testing process is simple to control, but the total testing time increases significantly

Engineering Contradiction:
Improvetesting timeVSAvoidtest pattern input complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-loading multiple test patterns into the test apparatus before beginning the actual testing process. This allows the test patterns to be ready in advance, eliminating the need to input them sequentially during testing, thereby reducing total testing time while maintaining controlled execution through automated sequencing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating multiple copies of test patterns and storing them in the test apparatus memory simultaneously. Instead of inputting one pattern at a time, multiple pattern copies are prepared in advance, allowing parallel preparation and sequential execution without repeated input operations, thus reducing time loss.

Inventive Principle:
Principle #26Copying

2Productivity

If test patterns are re-input for each test condition, then the testing process remains simple, but the setting time increases

Engineering Contradiction:
Improvetesting efficiencyVSAvoidsetting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements preliminary action by pre-configuring multiple test patterns in the apparatus before testing begins. This eliminates the need to re-input patterns for each test condition, as they are all prepared in advance. The automated execution system then sequentially applies these pre-configured patterns, significantly reducing setting time and improving testing efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The test apparatus performs self-service by automatically managing the sequential execution of pre-loaded test patterns without requiring manual re-input for each condition. The system autonomously retrieves and applies patterns from its memory in sequence, eliminating repetitive manual operations and reducing the time spent on setting up each test condition.

Inventive Principle:
Principle #25Self-service

3Duration of action of moving object

If manual input of test patterns is used, then the equipment remains simple, but the overall testing duration increases

Engineering Contradiction:
Improvetesting durationVSAvoidtest pattern execution automation
Core Design Contradiction:
Duration of action of moving objectVSExtent of automation

Solution Approach 1:

The patent applies self-service by enabling the test apparatus to automatically execute test patterns from its internal memory without requiring manual intervention for each pattern input. The system autonomously manages the sequencing and application of multiple test patterns, significantly reducing testing duration while implementing a practical level of automation that builds upon existing simple equipment architectures.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12181515B2Apparatus for performing multiple tests on a device under test
Publication Date: 2024.12.31 NAN YA TECH
  • US12181515B2 patent drawing
  • US12181515B2 patent drawing
  • US12181515B2 patent drawing

AI summary

An apparatus for performing multiple tests on a device under test (DUT) are provided. The apparatus includes at least one non-transitory computer-readable medium having stored thereon computer-executable instructions and at least one processor coupled to the at least one non-transitory computer-readable medium. The computer-executable instructions are executable by the at least one processor and cause the apparatus to perform operations of inputting a plurality of test patterns to a test apparatus, performing each of the plurality of test patterns on the DUT without interruption, and obtaining a respective result for the DUT in response to each of the plurality of test patterns.