Parallel TFT Pixel Electrode Drive for High-Current Displays

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Solution Overview

Problem

Existing electrophoretic display devices face challenges in efficiently driving pixel electrodes with high current while maintaining the integrity of transistors, as excessive current can lead to thermal degradation and transistor breakage due to the limited channel width to length ratio of semiconductor layers.

Innovation Solution

The design incorporates a semiconductor substrate with multiple transistors connected in parallel between the source line and pixel electrode, where each transistor has a channel region that wholly overlaps the gate line, allowing for increased channel width to maintain current flow without exceeding the desirable W/L ratio, thus reducing the risk of transistor failure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the channel width of the thin-film transistor is increased to increase current flow, then the current driving capability is improved, but the transistor becomes more susceptible to thermal degradation and breakage

Engineering Contradiction:
Improvecurrent driving capabilityVSAvoidtransistor reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The invention divides a single transistor into multiple transistors connected in parallel. Each transistor has a moderate channel width that maintains reliability, while the parallel configuration collectively provides the required current driving capability. This segmentation allows the system to achieve high power without individual transistors exceeding safe operating parameters.

Inventive Principle:
Principle #1Segmentation

2Power

If the channel width to length ratio is increased to allow higher current flow, then the current capacity is improved, but the transistor operates closer to failure thresholds

Engineering Contradiction:
Improvecurrent capacityVSAvoidthermal degradation risk
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

The patent segments the current path into multiple parallel transistor channels. Each transistor operates at a safer W/L ratio that avoids thermal degradation, while the aggregate current capacity of all parallel transistors meets the high current requirements. This distributes the thermal load and prevents any single transistor from operating in the dangerous high-power-density regime.

Inventive Principle:
Principle #1Segmentation

3Power

If multiple transistors are connected in parallel to increase current flow, then the current driving capability is improved, but the device complexity increases

Engineering Contradiction:
Improvecurrent driving capabilityVSAvoidtransistor configuration complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The invention merges multiple transistors into a unified parallel configuration that functions as a single current-driving unit. The transistors share common source and drain electrodes, and are controlled by a shared gate line, creating a modular structure that achieves high current capacity while maintaining relatively simple integration. This combining approach distributes current stress across multiple devices while presenting a unified interface to the rest of the circuit.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12148842B2Semiconductor substrate and display device
Publication Date: 2024.11.19 MAGNOLIA WHITE CORP
  • US12148842B2 patent drawing
  • US12148842B2 patent drawing
  • US12148842B2 patent drawing

AI summary

According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.