Parallel Tile Synchronization for Accurate Lithography Simulation

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Solution Overview

Problem

Conventional parallel computing solutions for large area lithography simulation face inefficiencies due to tile boundary inconsistencies, which arise from limited information exchange between neighboring tiles, leading to suboptimal results, especially at advanced technology nodes like 5 nm and beyond.

Innovation Solution

A synchronized parallel computing architecture where a manager machine oversees overall algorithms, and worker machines exchange intermediate results to synchronize simulation steps, preventing tile boundary inconsistencies by treating the integrated circuit design layout as a whole and using an underlying tiling scheme to smoothly combine results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional parallel computing solutions divide the layout into tiles for independent processing, then processing speed is improved, but tile boundary inconsistencies arise due to limited information exchange between neighboring tiles

Engineering Contradiction:

Improveprocessing speedVSAvoidsimulation accuracy at tile boundaries

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces a synchronization mechanism that acts as an intermediary between independently processing tiles. Manager machines coordinate intermediate results exchange between worker machines processing different tiles, enabling information flow across tile boundaries while maintaining parallel processing efficiency. This mediator resolves the contradiction by facilitating communication without serializing the entire computation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the large layout into multiple tiles that can be processed in parallel by different worker machines, improving processing speed. However, it combines segmentation with synchronization points where intermediate results are exchanged, allowing each tile to be independently processed while still maintaining global consistency through coordinated information exchange at boundaries.

Inventive Principle:

Principle #1Segmentation

2Productivity

If tiles are processed independently in parallel, then computational efficiency is improved, but information exchange between neighboring tiles is limited leading to boundary inconsistencies

Engineering Contradiction:

Improvecomputational efficiencyVSAvoidinformation exchange between tiles

Core Design Contradiction:

ProductivityVSLoss of information

Solution Approach 1:

The patent implements a feedback mechanism where intermediate results from each tile are exchanged and used to update subsequent processing. Worker machines send intermediate results to neighboring tiles through manager machines, creating a feedback loop that ensures information from one tile influences adjacent tiles, preventing information loss while maintaining parallel computational efficiency.

Inventive Principle:

Principle #23Feedback

3Manufacturing precision

If the entire layout is processed as a whole, then simulation accuracy is improved, but processing time increases significantly

Engineering Contradiction:

Improvesimulation accuracyVSAvoidprocessing time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent segments the entire layout into multiple independent tiles that can be processed simultaneously by different worker machines, dramatically reducing processing time compared to processing the entire layout as one unit. The segmentation is combined with synchronization mechanisms to maintain accuracy.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the benefits of independent tile processing with coordinated information exchange. By combining parallel processing of segmented tiles with synchronized intermediate result exchange, the system achieves both the speed of divided processing and the accuracy of holistic simulation.

Inventive Principle:

Principle #5Merging (Combining)

4Manufacturing precision

If OPC and ILT techniques are applied to compensate for lithography distortions, then pattern fidelity is improved, but process complexity increases

Engineering Contradiction:

Improvepattern fidelityVSAvoidOPC and ILT process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies OPC and ILT techniques to individual tiles rather than the entire layout, reducing the computational complexity of each optimization problem while maintaining overall pattern fidelity through synchronized intermediate result exchange between tiles.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11747786B2Synchronized parallel tile computation for large area lithography simulation

Publication Date: 2023.09.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.