Parallel-to-Serial Conversion Circuit for Integrated Circuits
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Solution Overview
Problem
High-speed integrated circuits face challenges in reducing access time and complexity due to physical limits, particularly in memory devices, where parallel-to-serial conversion increases complexity exponentially with the number of data bits outputted, leading to increased occupied area and complexity.
Innovation Solution
A parallel-to-serial conversion circuit with a simple configuration that uses a data transfer unit, data output unit, correlation signal generation unit, and pulse signal generation unit to manage data output across multiple data lines and transfer lines, adjusting transmission signal activation times based on latency and logic values to accommodate various burst lengths, such as 2N and non-2N data outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel-to-serial conversion is implemented within the integrated circuit, then data output speed is improved, but device complexity increases exponentially with the number of data bits
Solution Approach 1:
The conversion circuit is divided into multiple sub-circuits, each handling a specific portion of the parallel-to-serial conversion process. This segmentation allows the overall complex function to be broken down into manageable, less complex components that can be implemented more efficiently within the integrated circuit.
Solution Approach 2:
The patent utilizes the time dimension by employing multi-phase clock signals to control the sequential operation of conversion stages. By distributing the conversion process across different time phases rather than requiring all conversion logic to operate simultaneously, the spatial complexity is reduced while maintaining the required data output speed.
2Quantity of substance
If parallel-to-serial conversion circuit is expanded to handle more data bits, then data output capacity is improved, but occupied area increases
Solution Approach 1:
Multiple conversion functions are merged into a unified circuit structure that processes different data bits through shared resources. By combining common logic elements and control mechanisms that serve multiple data lines, the circuit achieves higher data output capacity without a linear increase in occupied area.
Solution Approach 2:
The conversion circuit is designed with universal components that can handle multiple data bits through time-multiplexed operation. Single-purpose logic elements are replaced with multi-functional units that can process different portions of parallel data at different time phases, reducing the total component count and occupied area.
3Ease of manufacture
If transmission signals are generated using clock division for 2N:1 conversion, then signal generation simplicity is improved, but adaptability to non-2N burst lengths deteriorates
Solution Approach 1:
The circuit employs dynamic control mechanisms that can adjust the operation mode based on the required burst length. By using control signals that can be configured for different burst lengths (2N or non-2N), the circuit maintains simplicity in signal generation while gaining the flexibility to adapt to various data output requirements through reconfigurable control logic.
Solution Approach 2:
The patent utilizes parameter changes in the control signals, specifically the latency value and logic value of transmission signals, to adapt the circuit behavior for different burst lengths. By modifying these parameters rather than changing the fundamental circuit structure, the system maintains signal generation simplicity while achieving versatility across different data output scenarios.
Data Source
AI summary
An integrated circuit includes a plurality of data lines on which data aligned by a plurality of pulse signals are loaded, a plurality of transfer lines, a data transfer unit configured to transfer the data of the plurality of data lines to the plurality of transfer lines in response to a correlation signal, a data output unit configured to output the data of the transfer line corresponding to a transmission signal activated among a plurality of transmission signals, a correlation signal generation unit configured to generate the correlation signal using a latency value and a logic value of one of the plurality of transmission signals when a command is inputted to the correlation signal generation unit, and a pulse signal generation unit configured to sequentially activate the plurality of pulse signals when the command is inputted.