Parallel Tomlinson-Harashima Precoder Architecture for High-Speed Communication
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Solution Overview
Problem
Designing a fast Tomlinson-Harashima precoder for high-speed applications is challenging due to its complex architecture with infinite or exponentially large output levels, making traditional pipelining and look-ahead techniques difficult to apply effectively.
Innovation Solution
Converting the Tomlinson-Harashima precoder to an equivalent IIR filter form, applying classical look-ahead techniques, removing compensation signals, and using precomputation to achieve a parallel design that reduces critical path computation time, resulting in a faster and more efficient parallel Tomlinson-Harashima precoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a straightforward implementation of the TH precoder is used, then the architecture is simple to implement, but it cannot be clocked at high speeds due to feedback loops
Solution Approach 1:
The TH precoder is divided into multiple parallel sub-precoders, each handling a portion of the input data. This segmentation allows the overall system to operate at higher clock speeds by distributing the computational load across multiple independent units that can be clocked faster individually.
Solution Approach 2:
The patent transitions from a sequential single-path implementation to a parallel multi-path architecture, effectively adding a dimensional aspect to the processing. By unfolding the feedback loop into multiple parallel forward paths, the system achieves higher operational speed while managing complexity through structured parallelism.
2Speed
If traditional pipelining and look-ahead techniques are applied, then speedup may be achieved, but it is difficult to apply effectively due to infinite or exponentially large output levels
Solution Approach 1:
The patent modifies the operational parameters of the modulo device by pre-computing and storing compensation values in lookup tables. This parameter transformation converts the problematic infinite/exponential output space into a manageable finite set of pre-calculated values, enabling effective application of pipelining and look-ahead techniques.
Solution Approach 2:
The patent performs pre-computation of compensation values and stores them in lookup tables before the actual precoding operation. This preliminary action eliminates the need for complex real-time calculations during the critical path, thereby enabling faster clocking and easier implementation of parallel processing techniques.
3Measurement precision
If the wordlength is increased to accurately represent the exponentially large output levels, then precision is improved, but the complexity and computation time increase exponentially
Solution Approach 1:
The patent pre-computes and stores compensation values in lookup tables during system initialization or fabrication. This preliminary computation eliminates the need for complex real-time arithmetic operations during data transmission, maintaining precision while dramatically reducing computation time and avoiding exponential complexity.
Solution Approach 2:
Instead of performing complex real-time calculations with large wordlength values, the patent creates a copy of pre-computed compensation values stored in lookup tables. This copying approach maintains the required precision by using accurate pre-calculated values while avoiding the time-consuming exponential complexity of real-time computation.
Data Source
AI summary
A method to design parallel TH precoders and a circuit architecture to implement parallel TH precoders have been presented. The parallel design relies on the fact that a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a compensation signal. The parallel design also relies on the fact that the compensation signal has finite levels. Therefore, precomputation techniques can be applied to calculate intermediate signal values for all possible values of the compensation signal.