Parallel Track-and-Hold Circuit for Higher ADC Data Rate
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Solution Overview
Problem
The speed of track-and-hold circuits is limited by the upper limit of clock signal frequency due to parasitic resistance and capacitance in transistors and wiring, restricting the data rate and ADC performance.
Innovation Solution
A track-and-hold circuit configuration that alternately switches between track and hold modes every half period of the differential clock signal using multiple transistors and capacitors, with a switch circuit controlled by differential clock signals, allowing for increased data rate without altering the clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal frequency is increased to speed up the track-and-hold circuit, then the data rate improves, but the parasitic resistance and capacitance in transistors and wiring cause the circuit to fail to operate properly
Solution Approach 1:
The patent divides the single track-and-hold circuit into multiple parallel circuits (first track-and-hold circuit and second track-and-hold circuit). Each circuit operates at a moderate clock frequency with manageable parasitic effects, while the combined output achieves higher effective data rate through parallel processing and selective switching based on clock phases.
2Productivity
If conventional single circuit configuration is used, then the circuit structure is simple, but the data rate is limited by the upper limit of clock signal frequency
Solution Approach 1:
The patent combines multiple track-and-hold circuits with complementary clock phases (VCK1 and VCK2) to achieve higher effective data rate. The circuits are merged through a switching mechanism that selects outputs based on clock phases, effectively doubling the data rate while keeping each individual circuit relatively simple.
Data Source
AI summary
A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.