Parallel Tracking Circuit for Memory Signal Margin Stabilization
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Solution Overview
Problem
In memory operations, such as SRAM, read and write signal margins decrease as operational supply voltage VDD decreases, leading to compromised speed performance, and existing approaches to improve speed in average logic and memory corners often sacrifice performance further.
Innovation Solution
A parallel tracking mechanism that includes both logic and memory transistors, with programmable delay elements, stabilizes read and write margins across various manufacturing process, voltage, and temperature corners, including low operational voltage conditions, by generating a reset signal that ensures successful data writing and reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If operational supply voltage VDD is decreased, then power consumption is reduced, but read and write signal margins decrease leading to compromised speed performance
Solution Approach 1:
The patent applies preliminary action by pre-charging the tracking bit line before the actual read/write operation. The tracking circuit pre-charges the bit line to a voltage level (e.g., 0.7VDD or 0.8VDD) before the main operation begins, ensuring that sufficient voltage margin is available for the subsequent read/write operation even when VDD is reduced. This pre-charging action occurs in advance and prepares the circuit for low-voltage operation.
Solution Approach 2:
The patent changes the voltage parameter of the tracking bit line differently from the main bit line. While the main bit line operates at standard voltage levels, the tracking bit line is charged to a scaled voltage level (0.7VDD or 0.8VDD) that is optimized for low-voltage operation. This parameter change allows the tracking circuit to operate reliably at reduced VDD while the main memory array can still function at standard voltages.
2Speed
If additional signal margins are added to improve speed performance in average logic and memory corners, then speed performance is improved, but power consumption increases and performance is compromised in fast logic and slow memory corners
Solution Approach 1:
The patent implements dynamics by making the tracking bit line charge voltage adaptive to different operating conditions. The tracking circuit dynamically adjusts the charge voltage based on the actual VDD level and operating corner (fast/slow logic, fast/slow memory). This dynamic adjustment allows the system to optimize signal margins for each specific corner without adding excessive margins for all corners, thereby improving speed performance where needed while maintaining power efficiency elsewhere.
Solution Approach 2:
The patent uses a tracking circuit that copies the essential functionality of the main memory bit line but operates independently with optimized parameters. The tracking bit line replicates the charge-discharge behavior of the main bit line but with scaled voltage levels and timing, allowing it to track and compensate for process, voltage, and temperature variations without affecting the main memory array. This copying approach enables corner-specific optimization without compromising overall system reliability.
Data Source
AI summary
A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit. The delay circuit is coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit, and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.