Parallel Training of DRAM Equalization Coefficients
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Solution Overview
Problem
The challenge lies in reducing the time required for training operations in semiconductor memory devices, particularly in high-capacity DRAM implementations, where multiple devices need to find optimal equalization coefficients, which is currently inefficient due to sequential processing.
Innovation Solution
A memory module with multiple semiconductor memory devices configured to perform simultaneous training operations, each equipped with a reception interface circuit that searches for and transmits selected equalization coefficients to a memory controller, allowing for concurrent training and reduced overall training time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential training operation is performed on multiple DRAMs, then each DRAM can be trained properly, but the total training time becomes very long
Solution Approach 1:
Multiple DRAM devices are merged into a single memory module that performs training operations simultaneously. The memory module includes multiple DRAMs (e.g., 4 ranks) that can be trained in parallel rather than sequentially, reducing total training time while maintaining proper training completion for each device.
Solution Approach 2:
The memory module is segmented into multiple independent DRAM devices, each with its own reception interface circuit capable of independent training operations. This segmentation allows each DRAM to be trained simultaneously without interfering with others, resolving the time contradiction.
2Quantity of substance
If multiple DRAMs are provided in a memory module for high capacity, then storage capacity increases, but training operation complexity increases
Solution Approach 1:
Each DRAM device in the memory module is equipped with a universal reception interface circuit that can independently perform training operations. This multi-functionality allows each DRAM to handle training autonomously, reducing the overall complexity management for the memory module while maintaining high capacity.
3Measurement precision
If training operations are performed sequentially on each DRAM, then training accuracy can be ensured, but productivity of memory module setup decreases
Solution Approach 1:
The training operations of multiple DRAMs are merged into a simultaneous process. The memory module performs training operations on all DRAM devices at the same time, maintaining training accuracy through independent reception interface circuits while dramatically improving setup productivity.
Solution Approach 2:
The training process continues simultaneously across all DRAM devices rather than pausing between devices. This continuous parallel action ensures that training accuracy is maintained for each device while maximizing the productivity and setup efficiency of the entire memory module.
Data Source
AI summary
A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.