Parallel Transistor Amplifier Sets for RF Power Efficiency
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Solution Overview
Problem
Conventional RF power amplifiers, such as those used in cellular communication systems, face inefficiencies at lower output power levels due to back-off power, limiting their ability to maintain high efficiency and linearity, especially in multi-carrier systems where high efficiency regions cannot be utilized.
Innovation Solution
A power amplifier integrated circuit design featuring multiple sets of transistor amplifiers configured to turn on at different power levels, combined using a combiner with spiral transmission lines, allowing for increased output power and gain flatness over a range of power levels and frequencies within a compact integrated circuit package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a conventional power amplifier operates at back-off power levels, then linearity is maintained, but efficiency deteriorates
Solution Approach 1:
The amplifier is divided into multiple parallel sets of transistor amplifiers, each set containing transistors with different turn-on power levels. This segmentation allows different transistor sets to operate at different power ranges, maintaining both linearity at back-off levels and efficiency at higher power levels.
Solution Approach 2:
The transistors are configured with different turn-on power levels by adjusting their bias conditions. This parameter change enables the amplifier to transition between different operating states, achieving high efficiency at back-off power levels while maintaining linearity when needed.
2Loss of energy
If a conventional Doherty amplifier uses parallel amplifiers with different turn-on power levels, then efficiency is improved, but output impedance isolation deteriorates
Solution Approach 1:
Output impedance isolation networks are introduced as intermediary components between the parallel amplifier sets. These networks prevent harmful impedance interactions between amplifiers while allowing their outputs to be combined, thus maintaining efficiency improvements without the detrimental side effects of impedance coupling.
3Power
If multiple parallel amplifier sets are combined, then output power is increased, but device complexity increases
Solution Approach 1:
Multiple amplifier sets are merged into a single integrated circuit package with shared biasing networks and output combining structures. This merging approach increases output power capability while minimizing the complexity increase by reusing common components across all amplifier sets.
Solution Approach 2:
The biasing networks and output combining structures serve multiple functions across different amplifier sets. These universal components reduce the overall device complexity by eliminating redundant elements while still supporting multiple parallel amplifier configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances efficiency and gain flatness over a wider range of power levels and frequencies, achieving higher output power and improved performance compared to conventional Doherty amplifier configurations, particularly at lower output power levels.
Implementation Method 1
A combiner is configured to receive and combine the amplified component output signals from the at least two sets of transistor amplifiers into an output signal. An integrated circuit package combines the power splitter, the at least two sets of transistor amplifiers, and the combiner.
Data Source
Figure 1A~1B
Figure 2~3
Figure 4~5
AI summary
A power amplifier circuit (200) includes a power splitter (212, 214, 216) that splits an input signal (202) into a plurality of component input signals (218 a-d). At least two sets of transistor amplifiers (220, 230) are each coupled in parallel to the power splitter (212, 214, 216) to receive and amplify different ones of the component input signals (218 a-d) to generate amplified component output signals. The two transistor amplifiers of each set of transistor amplifiers (220, 230) are configured to turn on at different power levels of the input signal relative to each other. A combiner (240) is configured to receive and combine the amplified component output signals from the at least two sets of transistor amplifiers (220, 230) into an output signal (204). An integrated circuit package (210) encloses the power splitter (212, 214, 216), the at least two sets of transistor amplifiers (220, 230), and the combiner (240).