Parallel Transistor Feedback Control for Uniform Switching
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Solution Overview
Problem
Parallel-coupled transistors in power stages experience unequal switching times due to process variations, leading to high in-rush current and voltage fluctuations, which cause stress and degradation, and existing solutions fail to effectively manage these issues in noisy environments.
Innovation Solution
The implementation of a system with parallel feedback pins coupled by a resistor to adjust voltage levels based on peak current values and designate a leader transistor, along with active drive controllers and fault monitoring systems, to reduce settling time and prevent faults from affecting other transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors are connected in parallel to increase current handling capability, then the power handling capacity is improved, but unequal switching times due to process variations cause high in-rush current and voltage fluctuations
Solution Approach 1:
The patent implements a feedback mechanism where the voltage bus terminal is coupled back to the gate driver through a feedback path. The gate driver monitors the voltage bus condition and adjusts the switching timing of parallel transistors accordingly, ensuring that transistors switch in a coordinated manner despite process variations. This feedback loop eliminates the in-rush current problem by preventing simultaneous switching of all parallel transistors.
Solution Approach 2:
The gate driver preemptively adjusts the switching timing of parallel transistors based on expected process variations. By introducing deliberate timing offsets before the transistors would naturally switch, the system prevents the harmful simultaneous switching condition from occurring in the first place, rather than reacting to it after it happens.
2Speed
If transistors switch simultaneously to reduce settling time, then the response speed is improved, but voltage fluctuations and transistor stress increase
Solution Approach 1:
The gate driver implements periodic, controlled switching of parallel transistors with deliberately staggered timing. Instead of attempting truly simultaneous switching, the system uses a periodic switching pattern where each transistor is activated in sequence with small time intervals, achieving both fast response and reduced voltage stress through rhythmic, coordinated operation.
3Manufacturing precision
If process variations are reduced to achieve uniform switching, then the switching uniformity is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The system uses the voltage bus itself as the feedback sensor, eliminating the need for separate high-speed voltage sensors on each transistor. The voltage bus naturally provides the feedback signal that indicates when switching is occurring, and the gate driver uses this self-provided information to adjust timing, reducing manufacturing complexity while achieving uniform switching.
Solution Approach 2:
The voltage bus serves multiple functions: it provides the power supply connection, acts as the feedback sensor for monitoring switching conditions, and serves as the communication medium between transistors and the gate driver. This multi-functionality reduces the number of separate components needed and simplifies the overall system architecture.
Data Source
AI summary
Methods, apparatus, systems and articles of manufacture are described to parallelize transistors. An example apparatus includes a first transistor on a first die and a second transistor on a second die. The example apparatus includes a parallel feedback terminal coupled to the first die and the second die and a current sensor including a first contact and a second contact. The example apparatus includes a resistor coupled to the current sensor and at least one of the switched terminal or a ground terminal. The example apparatus includes an active drive controller including a first input coupled to the resistor, a second input coupled to the parallel feedback terminal, and an output coupled to the parallel feedback terminal. The example apparatus includes an edge delay controller adapted to be coupled to a gate driver and an error amplifier, and a control contact adapted to be coupled to the gate driver.