Parallel Transistor Gate Interconnects for Ringing Suppression
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Solution Overview
Problem
Semiconductor devices with parallel transistors experience noise generation due to ringing during turn-on and turn-off, leading to EMI noise and inefficiencies in motor driving inverters, as existing solutions require different transistor structures to manage current distribution and switching speed.
Innovation Solution
A semiconductor device design featuring gate interconnects with varying resistance values per unit length, where the first gate interconnect has a higher resistance than the second gate interconnect, allowing for balanced current distribution and suppressed ringing by adjusting the number and configuration of interconnects to control the CR delay across transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a plurality of transistors are connected in parallel with identical structures, then current distribution should be uniform, but ringing occurs during switching due to parasitic LC causing EMI noise
Solution Approach 1:
The patent applies local quality by introducing different gate resistance values to different transistors within the parallel connection. Specifically, at least one transistor has a different gate resistance than others, creating localized variations in switching characteristics. This local differentiation suppresses ringing caused by parasitic LC by dampening oscillations in specific transistors, thereby reducing EMI noise while maintaining overall system reliability
Solution Approach 2:
The patent changes the gate resistance parameter of transistors to different values. By adjusting the gate resistance (Rg) of individual transistors, the switching speed and damping characteristics are modified. This parameter variation allows suppression of ringing oscillations during turn-on and turn-off transitions, reducing electromagnetic interference while maintaining controlled current distribution among parallel transistors
2Object-generated harmful factors
If gate resistance is increased to suppress ringing and delay switching speed, then EMI noise is reduced, but dead time period must be extended and motor driving efficiency drops
Solution Approach 1:
Instead of uniformly increasing gate resistance across all transistors, the patent applies different resistance values selectively. At least one transistor has a different gate resistance than others, allowing targeted suppression of ringing in specific transistors that contribute most to oscillations. This localized approach reduces overall dead time requirements and maintains higher motor driving efficiency while still suppressing harmful ringing
Solution Approach 2:
The patent optimizes gate resistance parameters by setting at least one transistor's gate resistance to a value different from others. This selective parameter adjustment achieves adequate damping of ringing oscillations without excessively delaying switching transitions across all transistors, thereby minimizing the required dead time and preserving motor driving efficiency
3Reliability
If different transistor structures are used to manage current distribution, then switching characteristics can be optimized, but current may concentrate on specific transistors
Solution Approach 1:
The patent implements local quality by varying gate resistance in individual transistors rather than using identical structures. This localized parameter differentiation allows each transistor to have optimized switching characteristics while the resistive differences naturally distribute current more evenly. The local variations prevent current concentration by creating slight differences in turn-on/turn-off timing and voltage distribution across the parallel transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses current concentration and ringing, maintaining transistor response characteristics while preventing through-current and optimizing dead time periods, thus reducing noise and improving efficiency in switching power supply devices.
Implementation Method 1
A resistance value of the first gate interconnect per unit length is larger than a resistance value of the second gate interconnect per unit length
Implementation Method 2
the product (charging and discharging time constant) of the resistance of a gate electrode and the capacitance between gate electrodes
Data Source
AI summary
A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP.