Parallel Transistor Configuration for I/O Output Slew Rate
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Solution Overview
Problem
In semiconductor integrated circuit devices, a decrease in I/O supply voltage reduces conductance and output slew rate, leading to slower data output rates, particularly in NAND flash memories where the P-type transistor's gate-source voltage decreases, affecting the data output rate.
Innovation Solution
A semiconductor integrated circuit device employs a combination of N-type and P-type transistors connected between output voltages and the pad, with an additional N-type transistor in parallel to the P-type transistor to maintain high switching rates even when the output high voltage decreases, ensuring faster data output by complementary operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the I/O supply voltage is decreased to reduce power consumption and noise, then power consumption and noise are reduced, but the conductance of the data output circuit decreases leading to slower data output rate
Solution Approach 1:
The patent changes the parameter of transistor conductance by introducing an additional N-type transistor in parallel with the P-type transistor. This parallel configuration increases the total conductance of the output circuit, allowing the data output rate to be maintained even when the I/O supply voltage is decreased for reduced power consumption and noise.
2Object-affected harmful factors
If the I/O supply voltage is decreased to reduce noise, then noise is reduced, but the gate-source voltage of the P-type transistor decreases reducing its conductance and output slew rate
Solution Approach 1:
The patent merges the P-type transistor and N-type transistor into a parallel configuration. The N-type transistor compensates for the reduced conductance of the P-type transistor at lower voltages, maintaining the overall output slew rate even when noise reduction requires lower I/O supply voltage.
3Device complexity
If a single P-type transistor is used for data output, then the circuit is simple, but the output slew rate decreases when I/O supply voltage decreases
Solution Approach 1:
The patent combines a P-type transistor and an N-type transistor in a parallel configuration. This merging of transistor types maintains high output slew rate across different voltage levels by leveraging the complementary characteristics of both transistor types, while adding only minimal circuit complexity.
Data Source
AI summary
This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.