Parallel Output Transistor LDO for Compact Phase Compensation

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Solution Overview

Problem

Existing linear power supply circuits face challenges in achieving phase compensation with reduced output capacitor capacitance without a significant increase in circuit area.

Innovation Solution

Incorporating a phase compensation circuit with a second output transistor, resistor, and capacitor, along with an operational amplifier to suppress potential differences between transistor gates, allowing for phase compensation without increasing circuit size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If phase compensation is implemented with traditional circuits, then phase compensation is achieved, but circuit area increases significantly

Engineering Contradiction:
Improvephase compensationVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the phase compensation function with the existing output transistor and output capacitor components. The second output transistor is connected in parallel with the first output transistor, and the phase compensation is achieved by utilizing the interaction between these transistors and the output capacitor, rather than adding a completely separate phase compensation circuit. This merging approach achieves phase compensation while minimizing additional circuit area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The output capacitor serves multiple functions: it acts as the output filter capacitor for voltage stabilization and simultaneously provides the capacitance necessary for phase compensation. The second output transistor also contributes to both current delivery and phase compensation through its interaction with the capacitor. This multi-functionality eliminates the need for dedicated phase compensation components, reducing overall circuit area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If output capacitor capacitance is reduced, then circuit compactness is improved, but phase compensation becomes difficult to achieve

Engineering Contradiction:
Improvecircuit compactnessVSAvoidphase compensation
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent changes the parameter configuration by introducing a second output transistor with specific characteristics (different width-to-length ratio) to work in parallel with the first output transistor. This parameter change enables the system to achieve phase compensation with a reduced output capacitor capacitance value, as the transistor configuration compensates for the reduced capacitance effect on phase margin.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If traditional phase compensation circuits are added, then phase stability is improved, but device complexity increases

Engineering Contradiction:
Improvephase stabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The phase compensation function is merged into the existing output stage architecture by adding a second output transistor in parallel with the first output transistor. This integration avoids the need for separate phase compensation circuits with multiple additional components, thereby improving phase stability while minimizing the increase in device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12498748B2Linear power supply circuit
Publication Date: 2025.12.16 ROHM CO LTD
  • US12498748B2 patent drawing
  • US12498748B2 patent drawing
  • US12498748B2 patent drawing

AI summary

A linear power supply circuit includes: an output stage provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied and including a first output transistor and a second output transistor connected in parallel with each other; a driver configured to drive the first and second output transistors based on the difference between a voltage based on the output voltage and a reference voltage; and a potential difference suppressor configured to suppress a potential difference between the control terminal of the first output transistor and the control terminal of the second output transistor.